Michael Duane

Improved p-ch MOS transistor performance with an arsenic supersteep retrograde channel profile

The benefits of super steep retrograde channel profiles on MOS transistor performance as reported in the literature have been inconsistent. This inconsistency is in part due to the sensitivity of the performance benefit to the process parameters and integration of the retrograde channel profile. As exhaustive study that integrated and optimized a p-ch arsenic retrograde channel profile transistor into a high performance sub 0.18micrometers transistor CMOS microprocessor process was performed. It was found that the dose and energy of the retrograde channel implant significantly affected the performance improvement obtained. A higher SSRC implant dose, or lower implant energy resulted in higher drive current for a given off current relative to a conventional channel profile control transistor. In addition, the improvement in the transistor linear current was even more significant. At IDOFF equals 1nA, the IDS and IDLIN improvement was approximately 10 percent and 16 percent, respectively. Improvement in transistor drive current also increased at higher drive current. The saturated threshold voltage and Drain Induced Barrier Lowering roll-off with effective channel length were superior for the retrograde channel profile versus the conventional channel profile transistor. Gate oxide reliability with the arsenic doping was also evaluated using Voltage Ramped Dielectric Breakdown (VRDB). It was found that the p-ch gate oxide capacitor VRDB failure rate with the arsenic retrograde channel doping profile was as good or better compared with the conventional phosphorous doped channel profile.

Re-examination of 2D dopant profiling needs

The National Technology Roadmap for Semiconductors (NTRS) has established some stringent requirements on two-dimensional dopant profiling. This work explores the reasons behind these metrology requirements, and also presents the difficulty of achieving these goals from the metrologist’s point of view. The goal of this paper is to present a more complete description of the metrology needs, including such issues as dopant statistics, surface profiling, active versus total concentrations, and physical regions of interest in a transistor in order to establish better metrology targets.

Line Length Dependencies in Interconnect Optimization

Metal line delay has become increasingly important for ULSI devices. Numerous expressions and software tools have been developed to describe interconnect delay as a function of the geometry and layout. Although many of these formulas have line length effects, this has not been explored in depth. Most software tools are either geared towards circuit designers, or involve more complex and CPU-intensive 3D modeling. In this work, PISCES (a 2D device simulator) was used to extract metal capacitance per unit length. We extend this approach for various lengths by creating a ladder network of the RC components and simulating in SPICE, or using simple closed-form Elmore delay equations. A new key result is that there are optimum metal line width/space for a fixed pitch and height/space ratios that are metal length dependent. For metal lines shorter than about 1500 micrometers , it is better to have narrower metal lines, and for lengths less than 500 micrometers , shrinking metal height is desirable because the penalty in resistance is more than compensated by the decrease in capacitance. For longer lines, the time delay is dominated by resistance, and wider, taller lines are better. Increasing metal spacing or reducing dielectric constant were beneficial for both long and short metal lines.

Device performance and optimization for 5th- and 6th-generation microprocessors

A family of CMOS processing technologies used to produce AMDs fifth and sixth generation microprocessors (K5 and K6) is described. Some of the issues that arose during the technology development and the transfer to manufacturing are also presented. Transistor performance is compared to literature results and shown to be best in its class.