Don Mullen

Design, modeling, and characterization of passive channels for data rates of 50 Gbps and beyond

The design of interconnects for links operating at 50 Gbps and beyond is very challenging. The loss, dispersion, and discontinuities along the signaling path have to be minimized over a wide frequency range. Frequency dependent material properties and surface roughness has to be accurately considered. The impacts of short via stubs that are ignored at lower data rates can severely degrade the signals when operating at higher data rates. In order to provide ways to mitigate these effects and optimize the performance of the system, it is primarily essential to correctly model and characterize the passive channel. In this paper, the modeling and characterization techniques that guarantee successful designs of passive channels for data rates of 50 Gbps and beyond will be presented. Detailed studies and measurement results on the effects of short via stubs are also presented.

Evaluation of a module based memory system with an LCP flex interconnect

An LCP flex interconnect is used to bypass the core vias and balls of the memory controller package, the PTH vias and traces of the FR-4 motherboard and memory module, and the traditional through-hole or SMT DIMM connector. A mating two-piece pin-grid array connector that can accommodate 36 differential pair signals is used to interface the flex to the memory controller package. On the memory side, the DRAM CSP package is directly soldered to the top layer of the flex and the bottom layer of the flex is soldered to the memory module via solder balls. Controller and memory test chips that are capable of operating in the 10 to 16 Gbps range are used for evaluating the possible data rates for 6″ and 12″ long flex links. The system margins are compared to a 3″ long motherboard-soldered memory system that was shown to operate at 16 Gbps.

Design and assembly of a double-sided 3D package with a controller and a DRAM stack

The microelectronic packaging field is moving into the third dimension for miniaturization, low power consumption, and better performance. In this paper, we present a double-sided flip-chip organic substrate with a memory controller on one side of the package, and 3D stacked disaggregated memory chips on the other side of the package. This design allows the controller to interface with the DRAM stack directly through the substrate providing the shortest possible interconnect path, and thus achieving the fastest signaling speed. However, this double-sided flip chip on organic substrate also causes yield, assembly, test, and reliability challenges. In order to optimize the assembly process, a sequential 3D finite-element model was developed to simulate the package assembly process. In these simulations, various assembly process sequences were simulated with different conditions and materials. In addition, a probing test model was also built to study the connectivity of the Land Grid Array (LGA) pin array with the PCB sockets. Results show that the careful selection of assembly steps and package materials are crucial for the successful package assembly and also important for the probing test.

Signal and power integrity analysis of a 256-GB/s double-sided IC package with a memory controller and 3D stacked DRAM

This paper presents signal and power integrity analysis of a double-sided flip-chip package. A memory controller is attached on one side of the organic substrate, and 3D-stacked, disaggregated memory chips, integrated with through silicon vias (TSVs), are connected on the opposite side. The signaling path of this 3D memory system consists of a short channel consisting of wafer-level redistribution layer (RDL) traces and small TSV vias. The signal integrity is not a source of concern for this extremely short channel; power integrity, however, poses significant challenges and consequently can limit the achievable data rate of this system. The double-sided flip-chip packaging p resents unique challenges in the design of l o w-impedance the power delivery network (PDN) and circuit design with low-sensitivity to power supply noises. All physical layers are code sign to optimize the integrated 3D package within electrical and manufacturing constraints in conjunction with robust circuit design that meets the power constraint. The detailed signal integrity analysis is presented to design robust link with low-swing signals and power integrity analysis to optimize the PDN designs to meet the PDN impedance targets.

Application of the latency insertion method to electro-thermal circuit analysis

In this paper, a fast circuit simulation technique based on the Latency Insertion Method (LIM) is proposed for the electro-thermal analysis of circuits and high-performance systems. The method is applied to the modeling of on-chip and off-chip 3D-interconnect networks. The proposed method is shown to be capable of modeling both electrical and thermal phenomena occurring in high speed, high performance VLSI circuits at the pre-layout design stages.

Design of low cost QFP packages for multi-gigabit memory interface

The feasibility of implementing a 3.2Gb/s XDR™ memory interface using an ultra low-cost LQFP package is analyzed. The target application includes multimedia electronics such as set-top boxes and HDTVs. Due to the large inductance of the LQFP package leadframes, power integrity is a major challenge for achieving high data rates. While single-ended signaling systems such as DDR and GDDR are very difficult to operate at multi-gigabit data rates using this highly inductive LQFP package, differential signaling systems such as an XDR memory interface is more immune to supply noise and it is suitable for high data rate operations. In this paper, we demonstrate that the XDR memory system with LQFP memory controller package can operate reliably at 3.2Gb/s. The proposed design is achieved by deploying a package/chip co-design approach, and by carefully balancing the supply-noise-induced jitter on different supply rails of the chip. Finally, the system function is validated under a test system with the proposed LQFP package and the model to hardware correlation at system level is presented.

High-performance, four-layer, wire-bonded, plastic ball grid array package for a 10 Gbps per lane backplane SerDes transceiver

A high-performance package design was required for a SerDes-to-SerDes Mux chip for backplane applications using eight 1.0-3.125 Gbps lanes on the system side and four 1.0-10.0 Gbps lanes on the backplane side. Cost and thermal targets required that this chip be built with wirebond assembly in a four-layer, 19/spl times/19mm 324 ball Plastic Ball Grid Array. Preliminary simulations were used to define package layout rules. Final 3-D simulations on the completed design showed that at 3.125GHz return loss was less than -20dB. At 10GHz, insertion loss was less than -1.0dB and crosstalk less than -50dB. Thermal simulations showed a thermal resistance of 11/spl deg/C/W using thermal vias, 1 m/s airflow, 2oz Cu power planes, a heat spreader, and 0.5mm solder balls.

Measurement and characterization of backplanes for serial links operating at 56 Gbps

The development of the next generation serial interfaces that operate between 50 Gbps and 60 Gbps is underway to deploy 400 Gb/s Ethernet systems. Design, analysis, and characterization of passive channels at these data rates are very challenging. Advanced modeling, analysis, and improved measurement techniques are required to accurately characterize high-speed links over broad frequency ranges. This paper describes the design and measurement used to characterize high-speed interconnects: boards, packages, and connectors including transition structures. Various interconnect components including several boards with various PCB laminates, backplanes with one and two connectors, straight through and orthogonal midplanes, chip-to-chip, and chip-to-module systems with transmitter and receiver packages are built and measured. Since both NRZ and PAM-4 signaling are presently under consideration for these new interfaces, the optimized interconnects are then analyzed using various equalization and these two signaling techniques at data rate of 56 Gbps. The resulting link performance is provided for the measured interconnect systems.

Thermal Analysis of Memory Module Using Transient Testing Method

The electrical transient testing method has become popular as a useful thermal analysis tool because of its accuracy, high repeatability and rich information content compared to the use of traditional steady state thermal characterization techniques. This paper presents a thermal study of a 16-chip memory module using transient testing. The two variables in this study are the thermal boundary conditions of and the power distribution within the module. By applying the method of network identification by deconvolution (NID) to a transient temperature measurement, the structure function can be identified, which is the dynamic thermal resistance versus capacitance along a particular heat flow path for a given boundary condition and power distribution. Comparisons of the structure functions reveal differences in the heat flow paths for the cases of one chip and multiple chips dissipating heat. Transient testing have been successfully used on a three-dimensional memory module, and determined the contributions to the overall dynamic thermal resistance by each of the components including the heat spreader (HS), socket and even thermal interface material (TIM). This information about a 3D assembly is often difficult to obtain using steady state techniques. Thermal engineers can use such information to differentiate the relative merit of materials and heat transfer mechanisms in a cooling solution to optimize the overall thermal budget.