Ravi Kollipara

Common-mode backchannel signaling system for differential high-speed links

Common-mode signaling is effectively used to create a backchannel communication path over the existing pair of wires for a self-contained adaptive differential high-speed link transceiver cell. A transceiver chip was designed in 0.13 /spl mu/m CMOS to demonstrate the feasibility of simultaneous differential and common-mode signaling. The design uses a three-level return-to-null signaling scheme with simultaneous voltage and timing reference extraction, to minimize the hardware costs and achieve robust operation for sending update information from receiver to the transmitter. The measured results indicate that this backchannel achieves reliable communication without noticeable impact on the forward link for bandwidths up to 50MHz and swings of 20-100mV.

A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques

A 5 Gb/s source-synchronous signaling system was developed utilizing a new clock/data skew minimization technique. The method incorporates a transmit clock delay line and integrating receiver yielding an increased tolerance to high frequency transmit source jitter. The system has the potential to support rapid turn-on without the clock buffer latency of conventional source-synchronous systems. A second method to minimize clock distribution delays with embedded clocking via superposition of clock in the common-mode across two differential pairs was also explored. A test device was fabricated in TSMCs 40 nm LP CMOS process and performance measurements indicate substantial margin improvements, even when the matched source-synchronous system is subjected to realistic source SJ and independent PSIJ noise. Comparable performance was also achieved with embedded common-mode clocking with matched peak swings, indicating it as a potential solution for pin-constrained designs.

Challenges and solutions for next generation main memory systems

Todays high performance computing memory systems mainly consist of with DDR3 DRAMs offering 800Mb/s to 1600Mb/s data rates. Extending the performance of these main memory systems beyond the current data rate is quite challengeable as the signal integrity issues with physical channel remains relatively constant compared to the device performance which improves as process advances. This paper presents three key technologies which help the current memory architecture to reach the data rates of 1600~3200Mb/s without sacrificing memory capacity, increasing power consumption, or switching to more advanced differential signaling. These key features include FlexPhase™ timing adjustment to eliminate trace length matching, dynamic point-to-point signaling to increase memory capacity at high data rates, and near ground signaling to reduce IO signaling power. This paper demonstrates the benefits of these features from signal and power integrity point of view.

Evaluation of high density liquid crystal polymer based flex interconnect for supporting greater than 1 TB/s of memory bandwidth

An LCP flex based interconnect that significantly improves the interconnect density and supports data rates in the range of 10 to 16 Gbps is evaluated to enable future high bandwidth module based memory systems without requiring complex equalization techniques. A mating two-piece, low- profile, high density and small insertion force connector is developed for interfacing the flex to a flip-chip package. The 216 pin connector can support 72 differential pairs in a 6 times 12 array.

Evaluation of a module based memory system with an LCP flex interconnect

An LCP flex interconnect is used to bypass the core vias and balls of the memory controller package, the PTH vias and traces of the FR-4 motherboard and memory module, and the traditional through-hole or SMT DIMM connector. A mating two-piece pin-grid array connector that can accommodate 36 differential pair signals is used to interface the flex to the memory controller package. On the memory side, the DRAM CSP package is directly soldered to the top layer of the flex and the bottom layer of the flex is soldered to the memory module via solder balls. Controller and memory test chips that are capable of operating in the 10 to 16 Gbps range are used for evaluating the possible data rates for 6″ and 12″ long flex links. The system margins are compared to a 3″ long motherboard-soldered memory system that was shown to operate at 16 Gbps.

Study of PCB Trace Crosstalk in Backplane Connector Pin Field

PCB traces in backplane are typically routed as striplines, which create near end crosstalk, but theoretically, no far end crosstalk. However, in practice, both near end and far end crosstalk introduced by via antipads and layer misalignment in the connector pin field due to manufacturing process variations can be significant. This paper presents an analysis for the first time of the PCB trace crosstalk in the connector pin field of high speed backplanes. Crosstalk from the adjacent differential pairs on the same layer and in particular, from neighboring layers is first modeled and simulated with the consideration of PCB design tolerances and routing constraints in the connector pin field. The model is then correlated with a 10ps edge TDR measurement. Finally, the simulated and measured results are provided to demonstrate the significance of the crosstalk due to connector pin field traces

Characterization of a low-power 6.4 Gbps DDR DIMM memory interface system

A memory system that meets the bandwidth, power efficiency, and capacity needs of future computing systems is presented in this paper. A 6.4 Gbps single-ended DDR memory interface for the controller and the DRAM was designed in a 28-nm CMOS process for a main memory system with dual-rank DIMMs. The architecture features a novel clocking scheme, per-pin timing adjustment, dynamic point-to-point signaling topology, and near ground signaling. The system V-T budget simulations and the characterization results of the fabricated memory interface are presented.

High-performance, four-layer, wire-bonded, plastic ball grid array package for a 10 Gbps per lane backplane SerDes transceiver

A high-performance package design was required for a SerDes-to-SerDes Mux chip for backplane applications using eight 1.0-3.125 Gbps lanes on the system side and four 1.0-10.0 Gbps lanes on the backplane side. Cost and thermal targets required that this chip be built with wirebond assembly in a four-layer, 19/spl times/19mm 324 ball Plastic Ball Grid Array. Preliminary simulations were used to define package layout rules. Final 3-D simulations on the completed design showed that at 3.125GHz return loss was less than -20dB. At 10GHz, insertion loss was less than -1.0dB and crosstalk less than -50dB. Thermal simulations showed a thermal resistance of 11/spl deg/C/W using thermal vias, 1 m/s airflow, 2oz Cu power planes, a heat spreader, and 0.5mm solder balls.

System design considerations for a 5Gb/s source-synchronous link with common-mode clocking

A 5Gb/s source-synchronous signaling system was developed utilizing embedded common-mode clocking technology to minimize clock distribution delays and to reduce the total pin count. The common-mode clocking scheme forwards the clock on the common mode of the differential data channels. In addition to the signal integrity issues present in differential signaling systems, the embedded common-mode clocking scheme presents additional challenges in system design. By means of impedance control for both common mode and differential mode, careful trace length matching, 5W spacing rule etc, we achieved good signal integrity and the link exhibits good margin. Mode conversion is one of the key issues in the common-mode clocking technology, and it is covered in detail. Measurement results show that the clocking scheme can tolerate −13dB mode conversion on both differential pairs at 5Gb/s.

Signal and Power Integrity Analysis of High-Speed Links with Silicon Interposer

Silicon interposers are frequently used in memory and network processor systems to closely integrate multiple chips and improve the performance of high-speed systems. The proximity provided by silicon interposer greatly improves bandwidth, power, and latency by simplifying communication and clocking of the links. However, the design of silicon interposer systems poses new challenges in managing the signal and power integrity of the systems. In signal integrity, the design of spiral inductors which are critical in high-speed links requires special consideration to minimize the interaction between the on chip spiral inductance and the low resistivity silicon interposer. In power integrity, the impact of on-interposer decoupling capacitors to suppress the mid-frequency noise depends on the design rules of the top layer of the silicon interposer. The resistive and capacitive characteristics of silicon interposer can determine the effectiveness of the decoupling capacitors placed on the interposer. Thus, careful analysis of on-die inductor and interposer decoupling capacitors is required.