Dave Secker

Design, modeling, and characterization of passive channels for data rates of 50 Gbps and beyond

The design of interconnects for links operating at 50 Gbps and beyond is very challenging. The loss, dispersion, and discontinuities along the signaling path have to be minimized over a wide frequency range. Frequency dependent material properties and surface roughness has to be accurately considered. The impacts of short via stubs that are ignored at lower data rates can severely degrade the signals when operating at higher data rates. In order to provide ways to mitigate these effects and optimize the performance of the system, it is primarily essential to correctly model and characterize the passive channel. In this paper, the modeling and characterization techniques that guarantee successful designs of passive channels for data rates of 50 Gbps and beyond will be presented. Detailed studies and measurement results on the effects of short via stubs are also presented.

On overcoming the limitations of single-ended signaling for graphics memory interfaces

In this paper, we explore the effectiveness of various solutions that can be applied to improve the performance of SE signaling at small incremental cost to the system. Specifically, we examine solutions for mitigating the impact of crosstalk, supply noise, and inter-symbol interference (ISI) to enable reliable communication over a graphics memory channel at 12.8-Gbps. We further compare measured silicon data from a 12.8-Gbps SE interface to a 20Gbps differential (DIFF) interface, implemented in the same silicon technology and sharing many of the critical circuits.

Design and analysis of a TB/sec memory system

The design and analysis of a Terabyte per second (TB/sec) memory system is presented. The interface technology utilizes a bi-directional low-swing differential signaling with a data transfer rate of 16 Gbps/pair. The memory system uses asymmetrical architecture where the timing adjustment and equalization circuits for both memory WRITE and READ are on the controller to reduce the memory cost. This paper describes the design and analysis employed to develop the memory interface using conventional and low-cost interconnect technologies. The design and characterization of the prototype system at component and system-level are presented and model to hardware correlations are discussed at component and system levels. System analysis is used to optimize and predict the yield of the system, to calculate system timing and voltage margins, and to verify targeted bit-error-rate (BER).

Design of low cost QFP packages for multi-gigabit memory interface

The feasibility of implementing a 3.2Gb/s XDR™ memory interface using an ultra low-cost LQFP package is analyzed. The target application includes multimedia electronics such as set-top boxes and HDTVs. Due to the large inductance of the LQFP package leadframes, power integrity is a major challenge for achieving high data rates. While single-ended signaling systems such as DDR and GDDR are very difficult to operate at multi-gigabit data rates using this highly inductive LQFP package, differential signaling systems such as an XDR memory interface is more immune to supply noise and it is suitable for high data rate operations. In this paper, we demonstrate that the XDR memory system with LQFP memory controller package can operate reliably at 3.2Gb/s. The proposed design is achieved by deploying a package/chip co-design approach, and by carefully balancing the supply-noise-induced jitter on different supply rails of the chip. Finally, the system function is validated under a test system with the proposed LQFP package and the model to hardware correlation at system level is presented.

Measurement and characterization of backplanes for serial links operating at 56 Gbps

The development of the next generation serial interfaces that operate between 50 Gbps and 60 Gbps is underway to deploy 400 Gb/s Ethernet systems. Design, analysis, and characterization of passive channels at these data rates are very challenging. Advanced modeling, analysis, and improved measurement techniques are required to accurately characterize high-speed links over broad frequency ranges. This paper describes the design and measurement used to characterize high-speed interconnects: boards, packages, and connectors including transition structures. Various interconnect components including several boards with various PCB laminates, backplanes with one and two connectors, straight through and orthogonal midplanes, chip-to-chip, and chip-to-module systems with transmitter and receiver packages are built and measured. Since both NRZ and PAM-4 signaling are presently under consideration for these new interfaces, the optimized interconnects are then analyzed using various equalization and these two signaling techniques at data rate of 56 Gbps. The resulting link performance is provided for the measured interconnect systems.