Dong-Woon Park

The Effect of Pad Properties on Planarity in a CMP Process

This study presents the effect of pad properties, such as elastic modulus and surface roughness, on planarity in a CMP process. A systematic method to measure planarization length , which represents the die-scale planarity in a quantitative manner, has been proposed. It has been shown that the planarization length is highly dependent on the bulk modulus of the pad. The effect of elastic modulus and roughness of the pad on dishing amount, which represents the feature-scale planarity, has been shown. Dishing amount is determined by the elastic modulus of the superficial layer of the pad, which is typically tens of microns thick, rather than by the bulk elastic modulus of the pad. A double layer pad model has been proposed based on the observed results, which can explain that the dishing amount is reduced by increasing elastic modulus of the pad superficial layer, or by decreasing the surface roughness of the pad.

Advanced module-based approach to effective CD prediction of sub-100nm patterns

In this article, an advanced module-based approach is introduced to simulate sub-100 nm patterns. Topography (TOPO), an in-house lithography simulator, consists of four basic modules: i) illumination, ii) mask, iii) imaging, and iv) resist. Since TOPO is module-based, it is convenient for user specific applications. The input parameter of illumination module is pupil intensity profile, which is measured using the transmission image sensor of ASML. In the mask kernel, mask corner rounding effect is considered while imaging module takes care of lens aberration and flare problems. Finally, the resist module uses Gaussian convolution model with the trade-off in mind between accuracy of full resist model and speed of Gaussian convolution model. As an application example, an iso-dense bias (ID bias) fitting is implemented for an ArF resist to image sub-100 nm patterns. Simulation results show that the fitting error meets the prediction accuracy target of International Technology Roadmap for Semiconductors 2002. The advanced module-based model using aerial image with measured pupil intensity profile and Gaussian convolution seems to be an effective way for the CD prediction of sub-100 nm patterns.

Modified procedure for evaluation of low-k1 process windows

For a lithography process, process windows are conventionally determined based on the amount of CD variation in a focus-exposure matrix (FEM). In a low-k1 region, however, a real process window can be smaller than is determined by the CD variation of FEM, due to a large mask error enhancement factor (MEEF). And the real process window cannot be determined by simply narrowing the process window obtained from a FEM, since MEEF itself is not a constant but a function of various process parameters. All the parameters which can affect MEEF should be considered carefully both in evaluation and in optimization of a real process window. Aerial-image base simulation was avoided in calculation of a process window because aerial-image based simulation cannot properly predict a process window even for simple 1-dimensional line-and-space patterns without introducing a fictitious variable like iso-focal bias, which cannot be extended to general 2-dimensional cases. In this study, a modified procedure for evaluation of process windows of critical layers has been proposed, and the process window was compared to the process window obtained by a conventional procedure. The proposed procedure has been implemented in our in-house lithography simulator to automatically process the evaluation of real process windows. Since the proposed procedure heavily relies on the accuracy of the lithography simulator, consideration of mask corner rounding effect and careful tuning of the physical properties of photoresists among others have also been included to guarantee the overall simulation accuracy.

The use of computational inspection to identify process window limiting hotspots and predict sub-15nm defects with high capture rate

As critical dimensions for advanced two dimensional (2D) DUV patterning continue to shrink, the exact process window becomes increasingly difficult to determine. The defect size criteria shrink with the patterning critical dimensions and are well below the resolution of current optical inspection tools. As a result, it is more challenging for traditional bright field inspection tools to accurately discover the hotspots that define the process window. In this study, we use a novel computational inspection method to identify the depth-of-focus limiting features of a 10 nm node mask with 2D metal structures (single exposure) and compare the results to those obtained with a traditional process windows qualification (PWQ) method based on utilizing a focus modulated wafer and bright field inspection (BFI) to detect hotspot defects. The method is extended to litho-etch litho-etch (LELE) on a different test vehicle to show that overlay related bridging hotspots also can be identified.

A method for generating assist-features in full-chip scale and its application to contact layers of sub-70nm DRAM devices

ArF is still being used as a main light source for lithography of critical layers due to development delay of alternative light sources. The resolution enhancement is therefore mainly depends on increasing the NA of the projection lens or on decreasing the k1 value. Depth-of-focus is becoming narrower in both the approaches than ever. It has been well-known that properly designed assist-features can improve the process window of lithography, but optimizing assist-features is generally not a simple task, unless the pattern area is small or all the patterns are well isolated so that the proximity effect can be safely ignored. It is challenging to generate assist-features automatically when the pattern area is not small or the patterns are not well isolated, both of which is not a case in todays memory devices. Todays memory chip has such a large pattern area that it easily occupies a large portion of the available imaging field of todays scanner. The proximity effect cannot be safely ignored because k1 factor is low in todays memory devices and the patterns are not isolated even in peripherals. A new method to generate assist-features has been internally developed. This method is based on optical simulation and utilizes the optical characteristic of the exposure tool to maximize the process margin, and is scalable to the full-chip scale. Side-lobes are automatically suppressed well under the imaging threshold. The total processing time is comparable to a usual model OPC processing time. The present paper demonstrates a test case of this new method to a contact layer of full-chip sub-70nm DRAM device and the improvement of depth-of-focus. The increased depth-of-focus was equivalent to 18% reduction of contact CD at the same depth-of-focus.

Investigation on polarization monitoring mask: pattern design and experimental verification

Since numerical aperture (NA) becomes greater than 1.0 in immersion lithography, polarization effect will be one of the critical issues in imaging performance. In patterning 40nm or smaller node with 193nm wavelength, transverse magnetic (TM) polarized beam does not contribute to image contrast. Hence most layers will require polarization controlled illumination to prevent the contrast degradation. For this reason, polarization controllability of illumination becomes one of considerable budget of critical dimension (CD) variation. For CD uniformity control of exposure tool and CD budget analysis, it is necessary to measure the polarization performance of illumination system. In-situ or special measurement tools are currently being developed to measure the polarization state of illumination and projection optics. However, each tool maker has its own measurement tool, and consequently in order to compare the polarization performance across different tools, a common measurement method is required. In this paper, a special mask pattern for monitoring polarization state of illumination has been designed. The polarization degrees have been measured for polarized illuminations of 193nm high NA tool. The pattern shape has been designed based on electric magnetic field (EMF) simulation utilizing the diffraction efficiency difference. The actual mask pattern sizes are measured to correct the measurement error. Differences between the EMF simulation and the real exposure results have been investigated for several illumination shapes and for different polarization status.

A simple and accurate resist parameter extraction method for sub-80-nm DRAM patterns

Due to the polarization effect of high NA lithography, the consideration of resist effect in lithography simulation becomes increasingly important. In spite of the importance of resist simulation, many process engineers are reluctant to consider resist effect in lithography simulation due to time-consuming procedure to extract required resist parameters and the uncertainty of measurement of some parameters. Weiss suggested simplified development model, and this model does not require the complex kinetic parameters. For the device fabrication engineers, there is a simple and accurate parameter extraction and optimizing method using Weiss model. This method needs refractive index, Dill’s parameters and development rate monitoring (DRM) data in parameter extraction. The parameters extracted using referred sequence is not accurate, so that we have to optimize the parameters to fit the critical dimension scanning electron microscopy (CD SEM) data of line and space patterns. Hence, the FiRM of Sigma-C is utilized as a resist parameter-optimizing program. According to our study, the illumination shape, the aberration and the pupil mesh point have a large effect on the accuracy of resist parameter in optimization. To obtain the optimum parameters, we need to find the saturated mesh points in terms of normalized intensity log slope (NILS) prior to an optimization. The simulation results using the optimized parameters by this method shows good agreement with experiments for iso-dense bias, Focus-Exposure Matrix data and sub 80nm device pattern simulation.