Jangho Shin

Experimental investigation of the impact of LWR on sub-100-nm device performance

Argon Fluoride (ArF) lithography is essential to develop a sub-100-nm device, however, line edge roughness (LER) and line width roughness (LWR) is playing a critical role due to the immaturity of photoresist and the lack of etch resistance. Researchers are trying to improve LER and LWR properties by optimizing photoresist materials and process conditions. In this paper, experiment results are presented to study the impact of LER and LWR to device performance so that the reasonable control range of LER and LWR can be defined. To implement the experiment, a 80-nm node of single negative-channel metal-oxide-semiconductor transistors were fabricated, which had various ranges of gate length, width, LER, and LWR. The amount of LER and LWR could be successfully controlled by applying different resist materials, defocus, and overetch time. Experimental results show that leakage current is significantly increased as LWR increases when the gate length is less than 85 nm. The main degradation is standard deviation of off-current (I/sub off/), and LWR is better representation to characterize a device performance.

Effect of line-edge roughness (LER) and line-width roughness (LWR) on sub-100 nm device performance

ArF lithography is essential to develop a sub-100 nm device, however, line edge roughness (LER) and line width roughness (LWR) is playing a critical role due to the immaturity of photoresist and the lack of etch resistance. Researchers are trying to improve LER/LWR properties by optimizing photoresist materials and process conditions. In this paper, experiment results are presented to study the impact of LER/LWR to device performance so that the reasonable control range of LER/LWR can be defined. To implement the experiment, 80 nm node of single NMOS transistors were fabricated, which had various range of gate length, width, and LER/LWR. The amount of LER/LWR could be successfully controlled by applying different resist materials, defocus, and over etch time. Experimental results show that leakage current is significantly increased when LWR is greater than 10 nm. In addition, it is observed that both threshold voltage and on-off current variation get increased exponentially as gate width decreases.

Study of process contributions to total overlay error budget for sub-60-nm memory devices

According to the 2006 International Technology Roadmap for Semiconductors, the overlay budget of 60nm memory devices is 11nm. To meet such a tight requirement, the total overlay error budget should be controlled carefully. There are many ways to analyze overlay budget; here, however, a simple but accurate methodology is introduced. In this study, total overlay error budget consists of four major contribution categories: scanner, process, metrology, and mask contributions. Scanner contributions are evaluated by measuring machine-to-machine overlay errors in the conventional way. Process contributions are estimated by inverse reactive-ion etch (RIE) lag and chemical mechanical polishing (CMP) erosion. Metrology contributions are evaluated by overlay metrology tools. Finally, mask contributions represent mask-to-mask misregistration. By applying this methodology to 60nm memory devices, it turns out that process contributions are more than 30% of the total overlay error budget for a contact layer. In this art...

Macro analysis of line edge and line width roughness

Line edge and line width roughness (LER/LWR) is commonly estimated by standard deviation sigma. Since the standard deviation is a function of sample line length L, the behavior of sigma(L) curve is characterized by the correlation length and roughness exponent. In this paper, an efficient and practical macro LER/LWR analysis is implemented by characterizing an arbitrary array of similar features within a single CD-SEM image. A large amount of statistical data is saved from a single scan image. As a result, it reports full LER/LWR information including correlation length, roughness exponent, sigma at infinite line length, and power spectrum. Off-line, in-house software is developed for automated investigation, and it is successfully evaluated against various patterns. Starting with the detailed description of the algorithm, experimental results are discussed.

Measurement technique of nontelecentricity of pupil-fill and its application to 60 nm NAND flash memory patterns

Various pupil-fill measurement techniques are evaluated to monitor non-telecentricity of an illuminator as followings: transmission image sensor (TIS) of ASML, source metrology instrument (SMI) of Litel, Fresnel zone plate (FZP) of Philips, and non-telecentricity measurement technique using traditional overlay marks, which is based on an idea that pattern shift is proportional to the amount of defocus. Based on aerial image simulation with measured non-telecentricity, its effect on sub-70 nm device patterning is discussed. Experimental data shows that some of pupil-fills appear more than 70 milli-radian of source displacement error and it may cause serious pattern shift and/or asymmetry. Detailed descriptions of measurement techniques and experimental results are presented.

Study of machine to machine overlay error for sub-60-nm memory devices

According to the 2007 international technology roadmap for semiconductors, the overlay budget of 60nm memory devices is 11.3nm. To meet such a tight requirement, each overlay error budget should be controlled carefully. It turns out that scanner contributions due to machine to machine overlay (MMO) error are nearly half of the total overlay error budget. In a conventional way, overlay errors are corrected by ten linear terms: offset x and y, wafer rotation x and y, wafer magnification x and y, shot rotation x and y, and shot magnification x and y. Especially for the shot correction, average correction values are applied commonly for all shots. MMO cannot be compensated by only linear correction to meet such a tight specification any longer. In this article, a grid matching strategy through per-shot-correction (PSC) is investigated so that scanner contributions are minimized. In PSC, shot correction is implemented for each shot with different correction parameter values. By matching wafer grids from machin...

Requirement of in-field illumination control for low k1 imaging below 0.3

As device production is performed towards limits of k1 process, many issues are caused by lowering k1 value, which has been considered negligible at higher k1 value. Among these passed-over problems, illumination control error such as non-telecentricity is currently investigated in-depth. Comparing with projection lens, illumination system is not well verified and the amount of aberration is quite larger. Consequently, illumination pupil-fill has different shape along field position resulting in in-field distribution with a degree, which may lead to considerable critical dimension (CD) difference. Therefore, the effect of errors in illumination system should be evaluated to determine the required controllability of illumination system for low k1 imaging. Illumination control error is represented by the deformation and movement of the intensity profile in pupil plane and it can be decomposed into blurring, intensity unbalance and telecentric error or axis tilt, and so forth. In this paper, these components are computationally modeled and the modeling is implemented using an in-house lithography simulator. Using the modeling, the functionality of each illumination error component on CD variation can be separately resolved. The analysis results presented in this paper provide the relationship between CD control and required illumination control, and the allowable amount of control error for illumination can be estimated.

Understanding the impact of source displacement error on sub-90nm patterns using a fresnel zone plate

Illumination source radiance distribution has a significant impact on vertical-horizontal bias and critical dimension (CD) variation on production wafers. In this article, the impact of source displacement error (SDE) on sub-90nm patterning is studied. A Fresnel zone plate (FZP) is adopted as a metrology to quantify the amount of SDE. Experimental data show that some of pupil-fills may have more than 50mrad of SDE and it could cause a serious pattern shift and/or CD asymmetry. A detailed description of FZP design specifications and application results are presented. Finally, SDE tolerance limits to print sub-90nm features are discussed.

Advanced module-based approach to effective CD prediction of sub-100nm patterns

In this article, an advanced module-based approach is introduced to simulate sub-100 nm patterns. Topography (TOPO), an in-house lithography simulator, consists of four basic modules: i) illumination, ii) mask, iii) imaging, and iv) resist. Since TOPO is module-based, it is convenient for user specific applications. The input parameter of illumination module is pupil intensity profile, which is measured using the transmission image sensor of ASML. In the mask kernel, mask corner rounding effect is considered while imaging module takes care of lens aberration and flare problems. Finally, the resist module uses Gaussian convolution model with the trade-off in mind between accuracy of full resist model and speed of Gaussian convolution model. As an application example, an iso-dense bias (ID bias) fitting is implemented for an ArF resist to image sub-100 nm patterns. Simulation results show that the fitting error meets the prediction accuracy target of International Technology Roadmap for Semiconductors 2002. The advanced module-based model using aerial image with measured pupil intensity profile and Gaussian convolution seems to be an effective way for the CD prediction of sub-100 nm patterns.

Characterization of pattern-placement error for sub-40-nm memory devices

Pattern-placement error (PPE) due to lens aberration is characterized for sub-40-nm memory devices. The amount of PPE depends on the feature size. PPE difference between memory cell and traditional box-in-box or advanced imaging metrology marks of KLA-Tencor Corporation is 4nm in the worst case for a given illumination condition. To avoid this kind of problem, a cell-like segmentation may be applied for alignment and overlay marks. However, the cell-like segmentation could degrade the alignment-signal intensity. In this article, a simple but effective methodology is introduced so that optimum segmentation size is determined. As a result, PPE error of alignment/overlay marks is close to memory cells with enough alignment-signal intensity.