Dongsheng Yang

A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique

This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 μm × 60 μm layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 μW DC power.

14.1 A 0.048mm 2 3mW synthesizable fractional-N PLL with a soft injection-locking technique

Phase-locked loops (PLLs) are a crucial building block in modern Systems-on-Chip (SoCs), which contain microprocessors, I/O interfaces, memories, power management, and communication systems. Fully synthesizable PLLs [1-2], designed using a pure digital design flow, have been proposed to reduce the design cost and allow easier integration. To achieve high-frequency resolution, PLLs are required to operate in fractional-N mode, in addition to integer-N mode. There are several architectures available [5-6] for realizing fractional-N operation. However, the existing topologies are not well suited for synthesis, as they require a time-to-digital converter (TDC) [3] and a digital-to-time converter (DTC) [4-5]. TDCs and DTCs are vulnerable to layout uncertainty, arising from automatic place and route (P&R), introducing linearity degradation and leading to poor in-band and out-of-band phase noise in PLLs. Injection locking is a promising technique for synthesizable PLLs. Unfortunately, it suffers from large spur caused by a periodic hard refresh, and limited fractional resolution, which is bounded to the inverse of the number of ring oscillator delay stages [6]. This paper describes a fully synthesizable fractional-N PLL with a soft injection-locking technique for smoothing switching and fine fractional resolution, and a cascading topology for suppressing the free-running oscillator phase noise over a wide loop bandwidth.

An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection

This paper presents an automatic place-and-routed two-stage fractional-N injection-locked PLL (IL-PLL) using soft injection technique for on-chip clock generation. Fabricated in a 65nm CMOS process, this prototype demonstrates a 3.6-ps integrated jitter at 1.5222 GHz and consumes 3mW leading to an FoM of -224.6 dB while only occupying an area of 0.048 mm2. It realizes the first fully synthesized fractional-N injection-locked PLL up-to-date.

An LC-DCO based synthesizable injection-locked PLL with an FoM of −250.3dB

This paper presents an LC-DCO based synthesizable injection-locked all-digital phase-locked loop. The superior noise performance of the LC-DCO enables the proposed synthesizable PLL to achieve top performance among the existing designs. Fabricated in a 65nm digital CMOS process, the chip occupies a core area of 0.12mm2. The measured integrated jitter is 0.142ps at a carrier of 3.0GHz while consuming a power of 4.6mW under 1V power supply. It achieves a figure of merit (FoM) of -250.3dB, which is the best for the synthesized PLL so far to the best knowledge of the authors.

An HDL-synthesized gated-edge-injection PLL with a current output DAC

This paper presents a small area, low power, fully synthesizable PLL with a current output DAC and an interpolative-phase coupled oscillator using edge injection technique for on-chip clock generation. A prototype PLL is fabricated in a 65nm digital CMOS process, achieves a 1.7-ps integrated jitter at 0.9 GHz and consumes 0.78 mW leading to an FOM of -236.5 dB while only occupying an area of 0.0066 mm2. It achieves the best performance-area trade-off.

A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI

A feedback current output digital to analog converter (DAC) is proposed to improve the linearity of frequency and reduce the power consumption in this synthesized PLL. All circuit blocks are implemented with standard cells from digital library and place-and-routed automatically without any manual routing. The proposed PLL has been fabricated in a 28 nm fully depleted silicon on insulator (FDSOI) technology. The measurement results show that this synthesized injection-locked PLL consumes 1.4mW from 1V supply while achieving a figure of merit (FoM) of −235.0 dB with 1.5 ps RMS jitter at 1.6GHz. This chip occupies only 64 μm × 64μm layout area with the advanced 28 nm FDSOI process. To the best knowledge of the authors, the PLL presented in this paper achieves the smallest area to date.

15.1 A 0.0066mm 2 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique

Phase-locked loops (PLLs) are widely used for clock generation in modern digital systems. All-digital PLLs have been proposed to address design issues in conventional analog PLLs. However, current all-digital PLLs require custom circuit design, and therefore cannot fully leverage advanced automated digital design flows. While fully synthesizable PLLs have been reported, they suffer from high power consumption and large area. This arises because each stage of the ring needs to have a large number of parallel tristate buffers/inverters in order to achieve the necessary frequency resolution. Moreover, custom-designed cells are required in prior synthesizable PLLs, introducing additional place-and-route (P&R) steps, leading to poor portability, integration, and scalability. To address these issues, this paper proposes a fully synthesizable PLL based solely on a standard digital library, with a current-output digital-to-analog converter (DAC) for maintaining frequency linearity and duty balance, an interpolative phase-coupled oscillator for minimizing the output phase imbalance from automatic P&R, as well as an edge injection technique for avoiding injection-pulse width issues.

An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation

This paper presents an HDL-synthesized injection-locked phase-locked loop using LC-based DCO for on-chip clock generation. The superior noise performance of the LC-DCO enables the proposed synthesizable PLL to achieve top performance among the existing designs. Fabricated in a 65nm CMOS process, this prototype demonstrates a 0.142ps integrated jitter at 3.0GHz and consumes 4.6mW while only occupying an area of 0.12mm2. It achieves a figure of merit (FoM) of −250.3dB, which is the best for the synthesized PLL up-to-date.

A 0.011 mm 2 PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI

This paper presents a fully-synthesizable clock and data recovery circuit using injection locking technique. The challenges presented by automated place and route for high speed applications is overcome using background calibration mechanism. The fully-synthesizable all-digital architecture presented in this work is fabricated in 28nm FDSOI technology. The system has a top data-rate of 10.05Gb/s while consuming 16mW power from 1.0V supply.