E. López-Morillo

A 1.2-V 140-nW 10-bit Sigma–Delta Modulator for Electroencephalogram Applications

This paper presents a second-order Sigma-Delta modulator for electroencephalogram applications with 10 bits of resolution, 1.2 V of supply voltage, and only 140 nW of power consumption over a bandwidth of 25 Hz. Low-voltage operation has been achieved using quasi-floating-gate-based circuits. The use of a new class-AB operational amplifier in weak inversion allows very low power consumption. Experimental results show an energy efficiency of 1.6 pJ per quantization level, making it the most energy-efficient converter reported to date in the very low signal bandwidth range.

A Low-Voltage Low-Power Front-End for Wearable EEG Systems

A low-voltage and low-power front-end for miniaturized, wearable EEG systems is presented. The instrumentation amplifier, which removes the electrode drift and conditions the signal for a 10-bit A/D converter, combines a chopping strategy with quasi-FGMOS (QFG) transistors to minimize low frequency noise whilst enabling operation at 1 V supply. QFG devices are also key to the A/D converter operating at 1.2 V with 70 dB of SNR and an oversampling ratio of 64. The whole system consumes less than 2 muW at 1.2 V.

A low-voltage low-power QFG-based Sigma-Delta modulator for electroencephalogram applications

A Sigma-Delta (SigmaDelta) modulator with 10 bits of resolution and only 55 nW power consumption for electroencephalogram (EEG) applications is presented. The overall modulator operates from 1.2 V using Quasi-Floating-Gates (QFG) based circuits. The system has been implemented in a standard 0.5-mum CMOS process. Post-layout simulations have been performed showing 70 dB of SNR with an oversampling ratio of 64.

Data Acquisition System based on Subsampling Using Multiple Clocking Techniques

This paper presents the implementation of a data acquisition system, where the folded thermal noise is reduced by using two consecutive subsampling processes. The presented implementation is used to test wideband multistandard receivers covering most of present communication standards. The proposed system converts a 20-MHz signal modulated with a programmable carrier frequency up to 6.5 GHz, so that it could be used as a universal receiver for software-defined radio applications. Experimental results show an effective number of bits larger than 9 bits up to 2.9 GHz, 8 bits up to 6.5 GHz, and 6.4 bits up to 20 GHz of input carrier frequency.

Subsampling Receivers with Applications to Software Defined Radio Systems

There are currently a large number of different communication standards, due to the widespread acceptance of wireless technologies. As a consequence, there is a tendency to design transceivers for multiple standards [1-8]. A similar problem arises in the test industry, where providers of testing and certification services to the wireless communication industry need multi-standard receivers, in order to reduce the cost in testing equipment.

A Very Low-Power Class AB/AB Op-amp based Sigma-Delta Modulator for Biomedical Applications

A sigma-delta (SigmaDelta) modulator with 8 bits of resolution and only 330 nW power consumption for a cardiac pacemaker is presented The overall modulator operates from 2.3 V down to 1.5 V supply using fully-differential class AB/AB amplifiers with transistors biased in weak inversion. The system has been implemented in a standard 0.5-mum CMOS process. Post-layout simulations have been performed showing 57 dB of SNR with an oversampling ratio of 32.

Compact low-power implementation for continuous-time ΣΔ modulators

This paper presents a low-area continuous time (CT) sigma-delta (@S@D) modulator implementation based on a local feedback. The proposed structure provides a very low impedance node without the need of classical op-amps, which leads to a reduction in power and area consumption. Two versions of a conventional first-order CT @S@D modulator prototype have been fabricated with the purpose of evaluating the idea. The modulator requirements have been set for a passive RFID tag with sensing capability application, so that achieving minimum active area and very low power consumption are the main objectives for the presented design. Experimental results of the first version of the modulator show 8 bits of Effective-Number-Of-Bits (ENOB) in a 25kHz signal bandwidth with 7@mW of power consumption. The proposed implementation has also shown to be very robust against supply voltage and bias current variations. A second approach has also been designed, using the same principle of operation, in order to increase the input voltage range without any power consumption penalty at the expense of decreasing the input impedance and stingily increased area. This second approach shows 9 bits of ENOB in the same signal bandwidth with a power consumption of 4.35@mW. A Figure Of Merit (FOM) of 0.267pJ/state has been achieved with a total area consumption (without pads) of 110@mmx125@mm in a 0.35@mm CMOS technology.

Low-Voltage Power-Efficient Amplifiers for Emerging Applications

Various design techniques aimed to obtain low-voltage power-efficient amplifiers are presented. Power efficiency is achieved by employing class-AB stages with high current efficiency based on these techniques. The use of resistive local common-mode feedback and quasi-floating gate transistors is covered in detail. Some applications of the amplifiers designed using these techniques are included.

Automatic Single Event Effects Sensitivity Analysis of a 13-Bit Successive Approximation ADC

This paper presents Analog Fault Tolerant University of Seville Debugging System (AFTU), a tool to evaluate the Single-Event Effect (SEE) sensitivity of analog/mixed signal microelectronic circuits at transistor level. As analog cells can behave in an unpredictable way when critical areas interact with the particle hitting, there is a need for designers to have a software tool that allows an automatic and exhaustive analysis of Single-Event Effects influence. AFTU takes the test-bench SPECTRE design, emulates radiation conditions and automatically evaluates vulnerabilities using user-defined heuristics. To illustrate the utility of the tool, the SEE sensitivity of a 13-bits Successive Approximation Analog-to-Digital Converter (ADC) has been analysed. This circuit was selected not only because it was designed for space applications, but also due to the fact that a manual SEE sensitivity analysis would be too time-consuming. After a user-defined test campaign, it was detected that some voltage transients were propagated to a node where a parasitic diode was activated, affecting the offset cancelation, and therefore the whole resolution of the ADC. A simple modification of the scheme solved the problem, as it was verified with another automatic SEE sensitivity analysis.

submitter : Design of a Radiation Hardened Power-On-Reset

In this paper, the design of a power-ON-reset intellectual property (IP) block for the RD53 collaboration, a radiation hardening by design circuit to withstand the High-Luminosity Large Hadron Collider tracker radiation environment, is presented. In this environment, the performance of the IP block under radiation must be ensured for a total ionizing dose up to 500 Mrad and possible ions interaction for a linear energy transfer of 15 MeV/cm2/mg. To verify the radiation hardness of the presented circuit, an automatic single-event effect sensitivity tool (Analog Fault Tolerant University of Seville Hardware Debugging System) has been used to perform a complete analysis over it, and also several experiments have been performed to test the designed blocks and obtain the final IP qualification.