Y.Z. Xu

A novel double RESURF LDMOS for HVIC's

Abstract The viability of a fully implanted double RESURF technology using a linearly varying doping of p-layer at the surface [Electron. Lett. 32 (12) (1996) 1092–1093] is demonstrated for the first time. Incorporating such a layer allows the drift region charge to be doubled without degradation of breakdown voltage. Experimental results of a high-voltage LDMOS in such a technology show a reduction in the on-resistance by one-half of that of a conventional RESURF based structure.

A segmented anode, npn controlled lateral insulated gate bipolar transistor

Abstract A fast switching area efficient segmented npn anode lateral insulated gate bipolar transistor is proposed. Segments of p + and npn are incorporated at the anode along the width in the third dimension instead of placing them linearly along the drift length of the device. The p-base parameters of the npn segment and the ratio of the p + and npn segments are found to strongly influence the switching behaviour.

Turn-on characteristics of polycrystalline silicon TFT's-impact of hydrogenation and channel length

Experimental measurements and two-dimensional (2-D) numerical simulation have been used to investigate the impart of the polycrystalline silicon (poly-Si) density of states (DOS) and channel dimensions on the transient response of poly-Si thin-film transistors (TFTs). TFTs exposed to different hydrogenation times were used to investigate the effect of the poly-Si DOS. The experimental results show that TFT turn-on time increases with increasing channel length and decreases with increasing hydrogenation time. For the first time, transient simulations were carried out using best fit poly-Si DOS distributions which were extracted numerically from DC transfer characteristics. The resulting simulations show excellent agreement with the experimental data. Degradation in the transient characteristic is thereby correlated with an increase In the poly-Si DOS.

A conductivity modulated high voltage polycrystalline silicon thin film transistor with improved on state and transient performance

A novel high voltage polycrystalline silicon thin film transistor, with an improved on state and transient performance, is presented in this report. The key features of the new structure are the combination of a p/sup +/ drain and a semi-insulating field plate which connects the gate to the drain. Minority carrier injection from the p/sup +/ drain increases the on state current by a factor of 5 and reduces the turn on time by over 10%. The minority carrier injection effects decay over sub-microsecond time scales.

A local charge control technique to improve the forward bias safe operating area of LIGBT

In this paper, for the first time, we demonstrate that incorporation of a shallow, lightly doped floating P-layer in the drift region of a high voltage CMOS/BiCMOS compatible, 500 V lateral insulated gate bipolar transistor can result in a significant improvement of its forward bias safe operating area. Detailed numerical calculations and analysis show that such an approach can enhance the on-state voltage handling capability without decreasing the breakdown voltage. The position of such a layer is shown to have a significant impact on the SOA performance of the device for the parameters considered. ” 2000 Elsevier Science Ltd. All rights reserved.

Novel dual gate high voltage TFT with variable doping slot

A novel high performance dual gated, glass compatible polycrystalline silicon HVTFT with blocking voltage in excess of 300 V is demonstrated. This device shows an order of magnitude improvement in the on-state performance in comparison to its offset drain (DG-OD) counterpart. The significantly enhanced performance of this dual gate device is due to an offset region doped through slots of reducing dimensions from the source (control gate) to the drain (sub-gate).

An investigation into the mechanisms limiting the safe operating area of a LIGBT in DI and DELDI technologies

Abstract The Forward Bias Safe Operating Areas (FBSOA) of 500xa0V LIGBTs in the Dielectric Isolation (DI) and the Double Epitaxial Layer Dielectric Isolation (DELDI) technologies are investigated by detailed numerical calculations. The FBSOA of a DELDI LIGBT is found to be wider than its DI counterpart. The factors limiting the sustaining voltage in the on-state have been identified. A shallow floating P-layer incorporated under the gate extension results in a significant improvement of the SOA in both the technologies.

Floating body induced transient characteristics in polycrystalline silicon TFTs

The floating body induced transient characteristics in polycrystalline silicon TFTs is reported. An obvious current surge, arising from the floating body effect, is observed. Using a 2D numerical simulator and comparisons to SIMOX FETs, the insight into the mechanisms governing the experimentally observed switching behavior of poly-Si devices is obtained. It is found that the defect states in poly-Si cause the current surge and exert an effect equivalent to doping in SIMOX FETs.

Stepped Gate Polysilicon Thin-Film Transistor for Large Area Power Applications

For the first time, we report a new poly-Si stepped gate Thin Film Transistor (SG TFT) on glass. The Density of States extracted from measured I-V characteristics has been used to evaluate the device performance with a two dimensional device simulator. The results show that the three-terminal SG TFT device has a switching speed comparable to a low voltage structure and the high on-current capability of a metal field plate (MFP) TFT and the potential for comparable breakdown characteristics.

The impact of field plate resistivity on the performance of a novel high voltage thin-film transistor incorporating a semi-insulating layer

The Semi-Insulating field plated High Voltage TFT (SI HVTFT) is a new poly-Si HVTFT structure with a much improved blocking capability and enhanced on-state performance [1][2]. The unique feature of the SI HVTFT is the semi-insulating amorphous oxygen-doped Si (SIAOS) field plate which connects the gate to the drain and reshapes the potential distribution in the offset region. The leakage current, flowing through the SIAOS field plate during device operation, determines device performance. In this paper, both experimental and 2-D simulation results for devices with different field plate conductivities are used to investigate the impact of the field plate properties on the performance of the SI HVTFT structure.