Kosta Selinidis

32 nm imprint masks using variable shape beam pattern generators

Imprint lithography has been included on the ITRS Lithography Roadmap at the 32, 22 and 16 nm nodes. Step and Flash Imprint Lithography (S-FIL ®) is a unique method that has been designed from the beginning to enable precise overlay for creating multilevel devices. A photocurable low viscosity monomer is dispensed dropwise to meet the pattern density requirements of the device, thus enabling imprint patterning with a uniform residual layer across a field and across entire wafers. Further, S-FIL provides sub-100 nm feature resolution without the significant expense of multi-element, high quality projection optics or advanced illumination sources. However, since the technology is 1X, it is critical to address the infrastructure associated with the fabrication of templates. For sub-32 nm device manufacturing, one of the major technical challenges remains the fabrication of full-field 1x templates with commercially viable write times. Recent progress in the writing of sub-40 nm patterns using commercial variable shape e-beam tools and non-chemically amplified resists has demonstrated a very promising route to realizing these objectives, and in doing so, has considerably strengthened imprint lithography as a competitive manufacturing technology for the sub 32nm node. Here we report the first imprinting results from sub-40 nm full-field patterns, using Samsungs current flash memory production device design. The fabrication of the template is discussed and the resulting critical dimension control and uniformity are discussed, along with image placement results. The imprinting results are described in terms of CD uniformity, etch results, and overlay.

Inspection of 32nm imprinted patterns with an advanced e-beam inspection system

We used electron beam (e-beam) inspection (EBI) systems to inspect nano imprint lithography (NIL) resist wafers with programmed defects. EBI with 10nm pixel sizes has been demonstrated and capability of capturing program defects sized as small as 4nm has been proven. Repeating defects have been captured by the EBI in multiple die inspections to identify the possible mask defects. This study demonstrated the feasibility of EBI as the NIL defect inspection solution of 32nm and beyond.

High Resolution Defect Inspection of Step and Flash Imprint Lithography for 32 nm Half-Pitch Patterning

Imprint lithography has been shown to be an effective method for the replication of nanometer-scale structures from an imprint mask (template) or mold. Step and Flash Imprint Lithography (S-FIL®) is unique in its ability to address both resolution and alignment. Recently overlay across a 200 mm wafer of less than 20nm, 3σ has been demonstrated. Current S-FIL resolution and alignment performance motivates the consideration of nano-imprint lithography as a Next Generation Lithography (NGL) solution for IC production. During the S-FIL process, a transferable image, an imprint, is produced by mechanically molding a liquid UV-curable resist on a wafer. Acceptance of imprint lithography for CMOS manufacturing will require demonstration that it can attain defect levels commensurate with the requirements of cost-effective device production. This report summarizes the result of defect inspections of wafers patterned using S-FIL. Wafer inspections were performed with KLA Tencor- 2132 (KT-2132) and KLA Tencor eS23 (KT-eS32) automated patterned wafer inspection tools. Imprint specific defectivity was shown to be ≤3 cm-2 with some wafers having defectivity of less than 1 cm-2 and many fields having 0 imprint specific defects, as measured with the KT-2132. KT eS32 inspection of 32 nm half pitch features indicated that the random defectivity resulting from the imprint process was low.

Nanoscale magnification and shape control system for precision overlay in jet and flash imprint lithography

Jet and flash imprint lithography steppers have demonstrated unprecedented capability for patterning of sub-25-nm features for semiconductor manufacturing. A critical requirement for such patterning is the ability to overlay one layer of a device to a previously printed layer. In this paper, the design and development of a nanoprecision mask magnification/shape control system (MSCS) for the unique requirements of imprint-based overlay is presented. Imprint specific topics such as in-liquid overlay and distortions, and on-tool overlay metrology are discussed. The MSCS presented here has demonstrated 10-nm mix and match overlay (mean + 3 sigma) capability that approaches performance of state-of-the-art photolithography tools.

Automated imprint mask cleaning for step-and-flash imprint lithography

Step-and-Flash Imprint Lithography (S-FIL) is a promising lithography strategy for semiconductor manufacturing at device nodes below 32nm. The S-FIL 1:1 pattern transfer technology utilizes a field-by-field ink jet dispense of a low viscosity liquid resist to fill the relief pattern of the device layer etched into the glass mask. Compared to other sub 40nm CD lithography methods, the resulting high resolution, high throughput through clustering, 3D patterning capability, low process complexity, and low cost of ownership (CoO) of S-FIL makes it a widely accepted technology for patterned media as well as a promising mainstream option for future CMOS applications. Preservation of mask cleanliness is essential to avoid risk of repeated printing of defects. The development of mask cleaning processes capable of removing particles adhered to the mask surface without damaging the mask is critical to meet high volume manufacturing requirements. In this paper we have presented various methods of residual (cross-linked) resist removal and final imprint mask cleaning demonstrated on the HamaTech MaskTrack automated mask cleaning system. Conventional and non-conventional (acid free) methods of particle removal have been compared and the effect of mask cleaning on pattern damage and CD integrity is also studied.

Inspection of imprint lithography patterns for semiconductor and patterned media

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Acceptance of imprint lithography for manufacturing will require demonstration that it can attain defect levels commensurate with the requirements of cost-effective device production. This work summarizes the results of defect inspections of semiconductor masks, wafers and hard disks patterned using Jet and Flash Imprint Lithography (J-FILTM). Inspections were performed with optical and e-beam based automated inspection tools. For the semiconductor market, a test mask was designed which included dense features (with half pitches ranging between 32 nm and 48 nm) containing an extensive array of programmed defects. For this work, both e-beam inspection and optical inspection were used to detect both random defects and the programmed defects. Analytical SEMs were then used to review the defects detected by the inspection. Defect trends over the course of many wafers were observed with another test mask using a KLA-T 2132 optical inspection tool. The primary source of defects over 2000 imprints were particle related. For the hard drive market, it is important to understand the defectivity of both the template and the imprinted disk. This work presents a methodology for automated pattern inspection and defect classification for imprint-patterned media. Candela CS20 and 6120 tools from KLA-Tencor map the optical properties of the disk surface, producing highresolution grayscale images of surface reflectivity, scattered light, phase shift, etc. Defects that have been identified in this manner are further characterized according to the morphology

Cleaning of step-and-flash imprint masks with damage-free nonacid technology

Step-and-flash imprint lithography S-FIL ® is a promising li- thography strategy for semiconductor manufacturing at device nodes be- low 32 nm. The S-FIL 1:1 pattern transfer technology utilizes a field-by- field ink jet dispense of a low-viscosity liquid resist to fill the relief pattern of the device layer etched into the glass mask. Compared to other sub-40-nm critical dimension CD lithography methods, the resulting high resolution, high throughput through clustering, 3-D patterning capa- bility, low process complexity, and low cost of ownership of S-FIL makes it a widely accepted technology for patterned media as well as a prom- ising mainstream option for future CMOS applications. Preservation of mask cleanliness is essential to avoid the risk of repeated printing of defects. The development of mask cleaning processes capable of re- moving particles adhered to the mask surface without damaging the mask is critical to meet high-volume manufacturing requirements. We present various methods of residual cross-linked resist removal and final imprint mask cleaning. Conventional and nonconventional acid- free methods of particle removal are compared and the effect of mask cleaning on pattern damage and CD integrity is also studied.

High-resolution e-beam repair for nanoimprint templates

UV nanoimprint lithography (UV-NIL) is a high-throughput and cost-effective patterning technique for complex nanoscale features and is considered a candidate for CMOS manufacturing at the 22nm node and beyond. To achieve this target a complete template fabrication infrastructure including inspection and repair is needed. Due to the 1X magnification factor of imprint lithography the requirements for these steps are more challenging compared to those for 4X photomasks. E-beam repair is a very promising repair technology for high-resolution imprint templates. It combines the advantages of precise beam placement using fine resolution images and damage free repair by electron beam induced chemical reactions. In this work we performed template repair using a new test stand with improved beam and stage stability. Repeatability of 3D pattern reconstruction with main focus on shrunk lateral repair dimensions and height control was investigated. The evaluation was done on various features in a 40nm half pitch design. Additionally, the resolution capability of the new hardware was examined on selected programmed defects in a 32nm half pitch design. A first qualitative examination of the repaired template was done using top-view SEM images taken from the test stand before and after repair. The repaired template was then imprinted on 300mm silicon wafers, and the imprinted repaired defects were analyzed using a SEM Zeiss Ultra 60.

Inspection and repair for imprint lithography at 32 nm and below

Step and Flash Imprint involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed leaving a patterned solid on the substrate. Compatibility with existing CMOS processes requires a mask infrastructure in which resolution, inspection and repair are all addressed. The purpose of this paper is to understand the progress made in inspection and repair of 1X imprint masks A 32 nm programmed defect mask was fabricated. Patterns included in the mask consisted of an SRAM Metal 1 cell, dense lines, and dense arrays of pillars. Programmed defect sizes started at 4 nm and increased to 48 nm in increments of 4 nm. These defects were then inspected using three different electron beam inspection systems. Defect sizes as small as 8 nm were detected, and detection limits were found to be a function of defect type. Both subtractive and additive repairs were attempted on SRAM Metal 1 cells. Repairs as small as 32nm were demonstrated, and the repair process was successfully tested for several hundreds of imprints.

Electron beam inspection methods for imprint lithography at 32 nm

Step and Flash Imprint Lithography redefines nanoimprinting. This novel technique involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed leaving a patterned solid on the substrate. Compatibility with existing CMOS processes requires a mask infrastructure in which resolution, inspection and repair are all addressed. The purpose of this paper is to understand the limitations of inspection at half pitches of 32 nm and below. A 32 nm programmed defect mask was fabricated. Patterns included in the mask consisted of an SRAM Metal 1 cell, dense lines, and dense arrays of pillars. Programmed defect sizes started at 4 nm and increased to 48 nm in increments of 4 nm. Defects in both the mask and imprinted wafers were characterized scanning electron microscopy and the measured defect areas were calculated. These defects were then inspected using a KLA-T eS35 electron beam wafer inspection system. Defect sizes as small as 12 nm were detected, and detection limits were found to be a function of defect type.