Janko Versluijs

Manufacturability issues with double patterning for 50-nm half-pitch single damascene applications using RELACS shrink and corresponding OPC

A double patterning (DP) process is discussed for 50nm half pitch interconnects, using a litho-etch-litho-etch approach on metal hard mask (MHM). Since an 0.85NA immersion scanner is used, the small pitch of 100nm is obtained by DP, the small trenches are made by a Quasar exposure followed by a shrink technique. The RELACS® process is used, realizing narrow trenches with larger DOF and less LER. For mask making, a design split is carried out, followed by adjustments of the basic design to make the patterns more litho-friendly. Assist features are placed next to isolated trenches to ensure sufficient DOF. Furthermore, an adjusted OPC calculation is carried out, taking into account proximity effects of both the exposure and the subsequent shrink process. After mask fabrication, this DP process is used for a single damascene application, with BDIIx as low-k material and TaN or TiN as MHM. Various problems are encountered, such as CD gain of the trenches during both MHM etch steps, poisoning and BARC thickness variations due to topography during the second litho step. For all these problems, solutions or work-arounds have been found, After the second MHM-etch, the 50nm half-pitch pattern is transferred successfully in the underlying low-k material.

Double pattern EDA solutions for 32nm HP and beyond

The fate of optical-based lithography hinges on the ability to deploy viable resolution enhancement techniques (RET). One such solution is double patterning (DP). Like the double-exposure technique, double patterning is a decomposition of the design to relax the pitch that requires dual masks, but unlike double-exposure techniques, double patterning requires an additional develop and etch step, which eliminates the resolution degradation due to the cross-coupling that occurs in the latent images of multiple exposures. This additional etch step is worth the effort for those looking for an optical extension [1]. The theoretical k1 for a double-patterning technique of a 32nm half-pitch (HP) design for a 1.35NA 193nm imaging system is 0.44 whereas the k1 for a single-exposure technique of this same design would be 0.22 [2], which is sub-resolution. There are other benefits to the DP technique such as the ability to add sub-resolution assist features (SRAF) in the relaxed pitch areas, the reduction of forbidden pitches, and the ability to apply mask biases and OPC without encountering mask constraints. Similarly to AltPSM and SRAF techniques one of the major barriers to widespread deployment of double patterning to random logic circuits is design compliance with split layout synthesis requirements [3]. Successful implementation of DP requires the evolution and adoption of design restrictions by specifically tailored design rules. The deployment of double patterning does spawn a couple of issues that would need addressing before proceeding into a production environment. As with any dual-mask RET application, there are the classical overlay requirements between the two exposure steps and there are the complexities of decomposing the designs to minimize the stitching but to maximize the depth of focus (DoF). In addition, the location of the design stitching would require careful consideration. For example, a stitch in a field region or wider lines is preferred over a transistor region or narrower lines. The EDA industry will be consulted for these sound automated solutions to resolve double-patterning sensitivities and to go beyond this with the coupling of their model-based and process-window applications. This work documented the resolution limitations of single exposure, and double-patterning with the latest hyper-NA immersion tools and with fully optimized source conditions. It demonstrated the best known methods to improve design decomposition in an effort to minimize the impact of mask-to-mask registration and process variance. These EDA solutions were further analyzed and quantified utilizing a verification flow.

Double patterning scheme for sub-0.25 k1 single damascene structures at NA=0.75, λ=193nm

Using 193nm lithography at NA=0.75, the minimum pitch that can be obtained in a single exposure is 160nm for dark field structures that are used in single damascene interconnect processing. In order to evaluate the critical electrical parameters for the smaller technologies, a double patterning scheme has been developed to obtain electrical structures at pitches from 140nm down to 100nm. This corresponds to k1-factors of 0.27 to 0.19 for dense trenches. The designs have been split up into two layers at more relaxed pitch (twice the final pitch). The first step consists in patterning a small semi-isolated trench at this more relaxed pitch. Because of the limited resist resolution for semi-isolated trenches, shrink techniques such as resist reflow or RELACS are needed. After etching this first layer into a low-k material or metal hard mask, planarization of the topography is critical before performing the second exposure. The second exposure is then identical to the first one, but overlay to the first layer is extremely critical in order to get a reasonable process window. In this paper, we illustrate the feasibility of the double patterning technique for early sub-65nm-node evaluation of low-k materials. The resolution and processing limits will be shown for single layer resist processing with RELACS shrink for 193nm lithography at NA=0.75. The planarization for the second photo is done using organic BARC. We will also quantify the overlay requirements to measured and introduced overlay errors.

A novel plasma-assisted shrink process to enlarge process windows of narrow trenches and contacts for 45-nm node applications and beyond

Limits to the lithography process window restrict the scaling of critical IC features such as holes (contact, via) and trenches (required for interconnects and double patterning applications). To overcome this problem, contacts or trenches can be oversized during the exposure, followed by the application of a shrink technique. In this work, a novel shrink process utilizing plasma-assisted polymer deposition is demonstrated: a polymer is deposited on the top and sidewalls of photoresist by alternating deposition and etch steps, reducing the dimension of the lithography pattern in a controlled way. Hence very small patterns can be defined with wide process latitudes. This approach is generic and has been applied to both contacts and trenches. The feasibility of the plasma-assisted shrink technique was evaluated through extensive SEM inspections after lithography, after shrink, and after etch, as well as through electrical evaluations.

Patterning challenges in setting up a 16nm node 6T-SRAM device using EUV lithography

Today, 22nm node devices are built using 193nm immersion lithography, possibly combined with double patterning techniques. Some stretch till the 16nm node is feasible here, using double, triple or even quadruple patterning. Alternatively, extreme ultra violet (EUV) lithography is showing promising results, and is considered to be the most likely option for this last mentioned device node. Electrically functional 22nm node devices are already available, where EUV lithography is used for the definition of the back-end layers. Fewer results are published on the patterning of front-end layers using EUV lithography. In this work, EUV lithography is used for the patterning development of the first four critical layers (active or fin, gate, contact and metal1) of a 16nm node 6T-SRAM cell. For the first time, front-end layers will need to be printed, with EUV, and transferred into an underlying substrate. The need for optical proximity correction is checked and characterized for all layers.

Dielectric Reliability of 50 nm Half Pitch Structures in Aurora® LK

The dielectric reliability of Aurora® LK (k = 3.0) material has been evaluated on a 50 nm half pitch test structure. These were fabricated using a double patterning scheme and TiN metal hard mask. The introduction of a suitable post-etch residue removal step and close-coupled processing between Cu electroplating and chemical mechanical polishing were found to be key for achieving high yield. Median time-dependent dielectric lifetime of 10 years is reached at an electrical field of 1.4 MV/cm, comparable to earlier reported results with SiO2 as dielectric. The reliability performance is found to be significantly layout dependent with corners being weak points due to local field enhancement.

30nm half-pitch metal patterning using Moti CD shrink technique and double patterning

Double patterning lithography appears a likely candidate to bridge the gap between water-based immersion lithography and EUV. A double patterning process is discussed for 30nm half-pitch interconnect structures, using 1.2 NA immersion lithography combined with the MotifTM CD shrink technique. An adjusted OPC calculation is required to model the proximity effects of the Motif shrink technique and subsequent metal hard mask (MHM) etch, on top of the lithography based proximity effects. The litho-etch-litho-etch approach is selected to pattern a TiN metal hard mask. This mask is then used to etch the low-k dielectric. The various process steps and challenges encountered are discussed, with the feasibility of this approach demonstrated by successfully transferring a 30nm half-pitch pattern into the MHM.

15nm HP patterning with EUV and SADP: key contributors for improvement of LWR, LER, and CDU

This paper discusses the approach for patterning 15nm Half Pitch (HP) structures using EUV lithography combined with Self-Aligned Double Patterning (SADP). A stack composed of a double hard mask, which allows decoupling photoresist transfer and trim, and an α-Si mandrel, which offers better mechanical properties during the mandrel and spacer patterning, is proposed. A break-down study with the patterning steps was performed to investigate the key contributors for improvement of LWR, LER and CDU, targeting integrated solutions with lithography, etch, thin film deposition, and wet cleans for selected applications. Based on the optimization of these key patterning contributors, optimum LWR, LER and CDU at 15nm HP are demonstrated.

Integration and Dielectric Reliability of 30 nm Half Pitch Structures in Aurora® LK HM

Aurora® LK HM (k=3.2) material has been successfully integrated into 30 nm half pitch structures. This material outperforms Aurora® LK (k=3.0) in terms of breakdown field strength and mechanical properties. Scaling of the physical vapor deposition (PVD) based barrier/seed process and adjusting of the barrier chemical mechanical polishing (CMP) overpolish condition were yield enabling factors. No degradation of the breakdown field upon reducing half pitch is observed down to 30 nm for line lengths up to at least 1 mm. The median time-dependent dielectric breakdown (TDDB) lifetime, as evaluated on a 1 mm 35 nm half pitch parallel line structure, exceeds 10 years at an electrical field of 2.6 MV/cm.

A way to integrate multiple block layers for middle of line contact patterning

It is clear today that further scaling towards smaller dimensions and pitches requires a multitude of additional process steps. Within this work we look for solutions to achieve a middle of line 193i based patterning scheme for N7 logic at a contacted poly pitch of 40-45 nm. At these pitches, trenches can still be printed by means of double patterning. However, they need to be blocked at certain positions because of a limited line end control below 90 nm pitch single print. Based on the 193i patterning abilities, the proposed SRAM (Static Random Access Memory) cell requires 5 blocking layers. Integrating 5 blocking layers is a new challenge since down to N10 one blocking layer was usually sufficient. The difficulty with multiple blocking layers is the removal of the masked parts, especially in cases of overlap. As a solution a novel patterning approach is proposed and tried out on relaxed dimensions (patent pending). The proposed solution is expected not to be sensitive to the number of blocking layers used, and tolerates their overlap. The stack is constructed to be compatible with N7 substrates such as SiGe or P:Si. Experimental results of the stack blocking performance on relaxed pitch will be presented and discussed.