Umberto Gatti

Gain and offset mismatch calibration in time-interleaved multipath A/D sigma-delta modulators

We propose a digital background adaptive calibration technique for correcting offset and gain mismatches in time-interleaved multipath analog-digital (A/D) sigma-delta (/spl Sigma//spl Delta/) modulators. The proposed technique allows us to cancel the spurious tones introduced by offset and gain mismatches among the paths only by processing the digital output, without interfering with the operation of the modulator. This solution is also effective for any other time-interleaved A/D converter topology. Simulation results on a high-performance four-path bandpass /spl Sigma//spl Delta/ modulator, operating on a 5-MHz band at a clock frequency of 320 MHz, demonstrate the effectiveness of the proposed calibration technique, which allows us to achieve significant improvements of the signal-to-noise ratio and the spurious-free dynamic range in the presence of mismatches.

A novel CMOS linear transconductance cell for continuous-time filters

A novel tunable transconductance cell with extended linearity is described. It is based on the use of the transconductance of an MOS transistor operated in the triode region. High linearity of the cell is achieved by maintaining both drain-to-source and source-to-body voltages of the transistor constant by means of a very simple feedback loop. The tuning of the transconductance cell is obtained by adjusting the current delivered by a current source. The cell also provides high operation speed. The circuit is suitable for the design of high-performance, high-frequency, continuous-time filters. It is shown that, when the cell is used in a fully differential configuration, harmonic distortion as low as 0.3% can be achieved for processed signals with a peak amplitude of 3 V.<<ETX>>

A wide-band 280-MHz four-path time-interleaved bandpass sigma-delta modulator

This paper describes a 0.35-/spl mu/m CMOS fourth-order bandpass analog-digital sigma-delta (/spl Sigma//spl Delta/) modulator for wide-band base stations receivers. The modulator, based on a time-interleaved four-path architecture, achieves an equivalent sampling frequency of 280 MHz, although the building blocks operate at only 70 MHz. In measurements, the prototype chip achieves a dynamic range of 72 dB (12 bits of resolution) with a signal bandwidth of 4.375 MHz centered around an intermediate frequency of 70 MHz. The measured spurious-free dynamic range is 69 dB. The /spl Sigma//spl Delta/ modulator dissipates 480 mW from a 3.3-V supply, including voltage reference buffers and output pads with high-driving capabilities, and occupies 20 mm/sup 2/ of silicon area.

A CMOS Current-Mode Magnetic Hall Sensor With Integrated Front-End

A Hall magnetic sensor working in the current domain and its electronic interface are presented. The paper describes the physical sensor design and implementation in a standard CMOS technology, the transistor level design of its high sensitive front-end together with the sensor experimental characterization. The current-mode Hall sensor and the analog readout circuit have been fabricated using a 0.18- μm CMOS technology. The sensor uses the current spinning technique to compensate for the offset and provides a differential current as an output signal. The measured sensor power consumption and residual offset are 120 μW and 50 μT, respectively.

From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications

Design automation for analog/mixed-signal (AIMS) circuits and systems is still lagging behind compared to what has been reached in the digital area. As System-on-Chip (SoC) designs include analog components in most cases, these analog parts become even more a bottleneck in the overall design process. The paper is dedicated to latest R&D activities within the MEDEA+ project ANASTASIA+. Main focus will be the development of seamless top-down design methods for integrated analog and mixed-signal systems and to achieve a high level of automation and reuse in the A/MS design process. These efforts are motivated by the urgent need to close the current gap in the industrial design flow between system specification and design on the one hand and block-level circuit design on the other hand. The paper will focus on three subtopics starting with the top-down design flow with applications from circuit sizing, design centering, and automated behavioral modeling. The next part focuses on modeling and simulation of specific functionalities in sigma-delta design while the last section is dedicated to a mixed-signal System-on-Chip design environment.

Full stacked layout of analogue cells

A program for the automatic layout of analogue CMOS cells using the full stacked approach is described. The stacked approach consists of the division of large transistors into several parallel elementary transistors, and of their accommodation in one or more parallel stacks made of the same number of transistors. The general rules for the design of stacked structures are discussed, and topological solutions of some popular schemes of operational amplifiers are presented. The stacked architecture is generated in a symbolic way, and it is automatically translated into the physical layout on the basis of the geometrical parameters and the technological design rules.<<ETX>>

An accurate CMOS sample-and-hold circuit

An accurate sample-and-hold (S/H) circuit implemented with a 2- mu m double-poly CMOS process is described. Competitive performance in terms of output swing, linearity, and clock feedthrough compensation was obtained using a new circuit topology. The sample and hold operates up to 1 MHz of sampling frequency with less than -60 dB of total harmonic distortion. The accuracy of the held step is better than 0.2 mV. The circuit dissipates 4 mW with a 5-V power supply. >

A SiGe BiCMOS burst-mode 155-Mb/s receiver for PON

In this paper we present an integrated 155 Mb/s burst-mode receiver (BMR) for passive optical network (PON) applications. The chip receives optical signals over a wide dynamic range (-27 dBm to 1 dBm) and temperature range (-40° C to +85° C). The chip was implemented using a sub-micron SiGe BiCMOS technology and occupies an area of 4.3 × 4.9 mm2with a power consumption of 500 mW from a supply voltage of 5 V. In the receiver analog front-end we used a low-noise wide-band transimpedance amplifier followed by a non-linear gain stage, to cover a wide signal range without changing the transimpedance gain. The circuit dynamically adjusts through a feedback loop the receiver threshold voltage, thus optimizing the pulse-width distortion and canceling the optical as well as the electrical offset voltages.

CMOS Vertical Hall Magnetic Sensors on Flexible Substrate

This paper presents the realization of different vertical Hall sensors (VHSs) implemented using a 0.18-μm CMOS technology and mounted on flexible substrates. Various geometries of VHS have been studied to obtain the optimum sensor device dimension and shape. COMSOL multiphysics simulation results are validated with respect to the electrical behaviour of an eight-resistor Verilog-A model implemented in Cadence environment. Simulation and measurement results are in good agreement. The use of polymeric foils and current spinning technique compensate for the effects caused by mechanical stress and possible fabrication imperfections. Measurement results for a low-offset basic VHS in planar state show a sensitivity of 59 ± 1 V(AT)-1 in voltage mode and of 8 ± 0.1 %T-1 in current mode.

A very flexible BiCMOS low-voltage high-performance source follower

This paper presents a new high performance source follower, which features very low output impedance and excellent driving capability, while only requiring a supply of one threshold plus two saturation voltages. In fact, its output conductance can be increased by a factor>500 with a suitable local loop, making this cell suitable for driving loads up to some tenths of ohms. Using this basic black, a novel class AB push-pull operational amplifier has been designed. It achieves good performance (output quiescent current=1.2 /spl mu/A, peak output current>200 /spl mu/A, max. capacitive load=1 nF), with a supply voltage of 1.3 V and a total power consumption of only 3.7 /spl mu/W.