Edorta Ibarra

A Step Forward Towards the Development of Reliable Matrix Converters

The matrix converter can be used in a wide range of applications. Nevertheless, it does not yet represent a sufficiently mature option for industrialization. In order to resolve this problem, this paper examines the hardware of the matrix converter and identifies all the circuits that should be included in this. It also quantifies the operating conditions and provides practical guidelines for the step-by-step design of a matrix converter. These considerations are validated with experimental results. In this way, it can be said that this paper represents a step forward toward the development of reliable matrix converters for real applications.

Matrix Converter Protection and Computational Capabilities Based on a System on Chip Design With an FPGA

The matrix converter (MC) presents a promising topology that needs to overcome certain barriers (complexity of the modulation and control techniques, protection systems, etc.) in order to gain a foothold in the industry. Traditionally, the MC has been controlled by means of a DSP, together with a field-programmable gate array (FPGA). The sole aim of the latter is to perform the safe commutation of the converter. This involves a waste of resources, as the excellent features of the FPGA are infrautilized by the control system. This paper deals with the implementation of the double-sided space vector modulation (DS SVM), commutation, reference-frame changes, and protection of the MC through a series of hardware blocks (cores) integrally implemented in an FPGA. The designed cores are technology-independent descriptions, which means that the developed design can be used in the FPGAs of any manufacturer. Moreover, the proposed design, which has been validated experimentally, has obviated the need to use a DSP. Likewise, given that all the processing capabilities have been integrated in a single chip, it can be said that an FPGA-based system on a programmable chip (SoPC) has been designed. Due to the computational capacity of the developed cores, processing time is reduced to the order of nanoseconds. This allows a response in real time and very high modulation frequencies can be attained. Moreover, these cores operate independently, and simultaneously, therefore obviating the need for sequential control and its resulting latencies and leading to an increase in the safety of the MC.

Generalized pulse-width-modulation to reduce common-mode voltage in matrix converters

In this paper a simple pulse-width-modulation strategy for matrix converters is studied. It takes advantage of the fact that the space vector modulation switching sequences for a matrix converter are the same as those created by the carrier-based modulation when an adequate zero-sequence component is injected into the carrier system references. A generalized equation for the zero-sequence component, which is a function of a distribution ratio of zero voltage vectors allows the pulse widths to be easily calculated, avoiding the complicated derivation of similar relations for matrix converters. Such generalization is possible by using the two-stage direct power converter topology and an adaptation of the duty cycles for the matrix converter switches. In particular, a modulation technique for reducing the common-mode voltage of the matrix converter is proposed based on this concept and comparison results are exposed, demonstrating its efficacy without a significant degradation of the input currents quality in the matrix converter.

A fault tolerant space vector modulation strategy for matrix converters

The topology of the Matrix Converter (MC) is promising because of its intrinsic advantages. Nevertheless, the MC is not as robust as other converters and therefore, under certain fault situations, the converter may be damaged. Certain applications of the MC, such as aeronautics, submarines, etc. require fault tolerant strategies that guarantee the continuous operation of the system under fault conditions. This article examines, in the first place, the behavior of the MC when it is protected by the clamp circuit and one of its switches is in open circuit due to a fault. In order to improve the fault tolerance of the MC, three SVM modulation variations are proposed. On the one hand, two of these variations guarantee the safety of the converter, but the THD of the synthesized voltages and currents is high. On the other hand, the third strategy enhances these and ensures the control of a PMSM in a fault situation.

Improvement of the Design Process of Matrix Converter Platforms Using the Switching State Matrix Averaging Simulation Method

The matrix converter (MC) is arousing considerable attention as an alternative for conventional ac/ac converters due to the advantages it offers. However, the control and modulation of this converter is complex. This, together with the fact that the MC usually operates at high modulation frequencies, makes the computational load of the platform to be simulated excessively high. All this makes the simulation time of models including the MC excessively long, even more so when both the transient and steady state of the system must be analyzed. This paper presents a new MC simulation technique called Switching State Matrix Averaging (SSMA). Although this is a fixed-step technique, a long simulation step can be used without forfeiting the accuracy of an ideal variable-step simulation. Likewise, the SSMA drastically speeds up the simulation, reducing the amount of required resources and the tuning time of the complex platforms in which the MC is used. A series of simulations has been performed in order to verify the proposed method. Moreover, a comparison between experimental and simulation results has been made, demonstrating the effectiveness of the proposed method.

Generalized PWM-Based Method for Multiphase Neutral-Point-Clamped Converters With Capacitor Voltage Balance Capability

This paper presents a generalized pulse width modulation (PWM)-based control algorithm for multiphase neutral-point-clamped (NPC) converters. The proposed algorithm provides a zero sequence to be added to the reference voltages that contributes to improve the performance of the converter by: 1) Regulating the neutral-point (NP) current to eliminate/attenuate the low-frequency NP voltage ripples; 2) reducing the switching losses of the power semiconductors; and 3) maximizing the range of modulation indices for linear operation mode. The control method is formulated following a carrier-based PWM approach. Hence, dealing with complex space-vector diagrams to solve the modulation problem for multiphase converters is avoided. The recursive approach means that it can be easily extended to n-phase converters without increasing the complexity and computational burden, making it especially attractive for digital implementation. The proposed method allows regulating the NP voltage without the need for external controllers; therefore, no parameter tuning is required. The algorithm has been tested in a four-leg NPC converter prototype performing as a three- and four-phase system and operating with balanced and unbalanced loads.

Matrix Converter: Improvement of the Space Vector Modulation via a new double-sided generalized Scalar PWM

This paper presents a particular modulation technique based on the generalized scalar pulse width modulation strategy for matrix converters. The objective of this solution is producing identical duty cycles and double-sided switching pattern that the well-known space vector modulation technique without the high memory requirements and the complex trigonometric operations of the last. Both the space vector and the proposed modulation techniques are simulated in a permanent magnet synchronous machine fed by a matrix converter. Its performances are compared with respect to total harmonic distortion (THD), execution times, number of operations and memory requirements. A wide range of simulations are carried out to verify the advantages of the proposed modulation technique when compared with the space vector modulator.

A new hardware solution for a fault tolerant matrix converter

The matrix converter (MC) presents a promising topology that needs to overcome certain barriers in order to gain a foothold in the industry. In some applications, where continuous operation must be insured under system failure, improved reliability of the converter is particularly of importance. In this sense, this article focuses on the study of a fault tolerant MC. The fault tolerance of a converter is characterized by its total or partial response in the case of a breakage of any of its components. Taking into consideration that virtually there is no work on fault tolerant MCs, this paper describes the most important studies in this area. On the other hand, this paper proposes a novel MC topology, which allows the flexible reconfiguration of this converter, once one or several of its semiconductors are damaged. In this way, the MC can continue operating at 100% of its performance without having to double its resources.

Maximum power extraction algorithm for a small wind turbine

Today, a characteristic of the operating regime of small wind turbines is that they do not obtain the maximum power efficiency. Taking into account that that the operability margin can, in general, be enhanced, this paper sets out to develop algorithms designed to extract the maximum power. First, an analysis is made of existing algorithms and as a result, a new algorithm is proposed to track the maximum power point (MPPT). This algorithm is based on an improvement in another previously defined in the literature. The proposed algorithm resolves the problem of Hill-climb searching algorithms in tracking the maximum power point, when the wind speed drops sharply. Lastly, the proposed algorithm is valid under any wind conditions and is, moreover, an economical alternative as it does not require any additional sensor for it to operate correctly.

A novel PMSM hybrid sensorless control strategy for EV applications based on PLL and HFI

In this paper, a novel hybrid sensorless control strategy for Permanent Magnet Synchronous Machine (PMSM) drives applied to Electric Vehicles (EV) is presented. This sensorless strategy covers the EV full speed range and also has speed reversal capability. It combines a High Frequency Injection (HFI) technique for low and zero speeds, and a Phase-Locked Loop (PLL) for the medium and high speed regions. A solution to achieve smooth transitions between the PLL and the HFI strategies is also proposed, allowing to correctly detect the rotor position polarity when HFI takes part. Wide speed and torque four-quadrant simulation results are provided, which validate the proposed sensorless strategy for being further implemented in EV.