Iñigo Martínez de Alegría

Matrix Converter Protection and Computational Capabilities Based on a System on Chip Design With an FPGA

The matrix converter (MC) presents a promising topology that needs to overcome certain barriers (complexity of the modulation and control techniques, protection systems, etc.) in order to gain a foothold in the industry. Traditionally, the MC has been controlled by means of a DSP, together with a field-programmable gate array (FPGA). The sole aim of the latter is to perform the safe commutation of the converter. This involves a waste of resources, as the excellent features of the FPGA are infrautilized by the control system. This paper deals with the implementation of the double-sided space vector modulation (DS SVM), commutation, reference-frame changes, and protection of the MC through a series of hardware blocks (cores) integrally implemented in an FPGA. The designed cores are technology-independent descriptions, which means that the developed design can be used in the FPGAs of any manufacturer. Moreover, the proposed design, which has been validated experimentally, has obviated the need to use a DSP. Likewise, given that all the processing capabilities have been integrated in a single chip, it can be said that an FPGA-based system on a programmable chip (SoPC) has been designed. Due to the computational capacity of the developed cores, processing time is reduced to the order of nanoseconds. This allows a response in real time and very high modulation frequencies can be attained. Moreover, these cores operate independently, and simultaneously, therefore obviating the need for sequential control and its resulting latencies and leading to an increase in the safety of the MC.

Three-Phase VSI Optimal Switching Loss Reduction Using Variable Switching Frequency

Loss reduction in converters is one of main targets in power electronics to obtain higher efficiency and lower thermal stress, which can enhance the lifetime of devices. This paper presents a variable switching frequency technique for switching loss reduction in a three-phase voltage source inverter, obtaining similar output current quality as that of a space vector pulse width modulation (SVPWM) algorithm. This type of optimization has not been applied for a three-phase system before. Simulation and experimental results are also shown. The output current ripple rms value of three-phase SVPWM is used as the optimization constraint. Results of the optimization of the switching losses with quality constraints in the switching frequency as the variable are presented for different load angles and compared with classical SVPWM. Experimental results show that this technique can save up to nearly

A new hardware solution for a fault tolerant matrix converter

19\%

Stability analysis and design of droop control method in dq frame for connection in parallel of distributed energy resources

in switching losses with similar total harmonic distortion of the output current, concluding that converter losses are reduced without reducing output current quality.

Maximum power extraction algorithm for a small wind turbine

The matrix converter (MC) presents a promising topology that needs to overcome certain barriers in order to gain a foothold in the industry. In some applications, where continuous operation must be insured under system failure, improved reliability of the converter is particularly of importance. In this sense, this article focuses on the study of a fault tolerant MC. The fault tolerance of a converter is characterized by its total or partial response in the case of a breakage of any of its components. Taking into consideration that virtually there is no work on fault tolerant MCs, this paper describes the most important studies in this area. On the other hand, this paper proposes a novel MC topology, which allows the flexible reconfiguration of this converter, once one or several of its semiconductors are damaged. In this way, the MC can continue operating at 100% of its performance without having to double its resources.

Circulating current control for modular multilevel converter based on selective harmonic elimination with ultra-low switching frequency

Droop control method is usually used when distributed energy sources are connected in parallel. The absence of communications between the distributed energy resources and its flexibility are some of its advantages. Moreover, a fictitious impedance can be added which improves the performance of the original technique. This fictitious impedance has to be properly designed in order to obtain a good stability and performance of the system. On the other hand, a restoration control that brings frequency and voltage amplitude of the microgrid to their nominal values is used in some cases. In this article, a linear model of a droop controlled microgrid with fictitious impedance and restoration control is implemented. Thanks to this linear model, an optimal fictitious impedance can be designed. Moreover, the influence of a proposed restoration control on the whole system can be studied. This way, the dynamic of the restoration control can be properly chosen. The stability as well as nominal values of frequency and voltage amplitude are guaranteed. Simulation results of the system confirm the validity of the proposed design.

(2N+1) Selective Harmonic Elimination-PWM for Modular Multilevel Converters: A Generalized Formulation and A Circulating Current Control Method

Today, a characteristic of the operating regime of small wind turbines is that they do not obtain the maximum power efficiency. Taking into account that that the operability margin can, in general, be enhanced, this paper sets out to develop algorithms designed to extract the maximum power. First, an analysis is made of existing algorithms and as a result, a new algorithm is proposed to track the maximum power point (MPPT). This algorithm is based on an improvement in another previously defined in the literature. The proposed algorithm resolves the problem of Hill-climb searching algorithms in tracking the maximum power point, when the wind speed drops sharply. Lastly, the proposed algorithm is valid under any wind conditions and is, moreover, an economical alternative as it does not require any additional sensor for it to operate correctly.

Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements

Multilevel converters (MCs) are utilized in medium voltage (MV) high power applications due to its higher efficiency than two level converters. On the other hand, modular multilevel converters (MMCs) provide several advantages with regard to other MCs, such as higher scalability, reliability and no requirement of a common DC capacitor. Particularly, low switching frequency modulations, such as (2N+1) selective harmonic elimination (SHE) - pulse width modulation (PWM), may improve the efficiency of MMCs when they are utilized in MV and high power applications, where the number of sub-modules is not high. This work presents a new circulating current control for MMC when (2N+1) SHE-PWM is utilized. Therefore, it is possible to operate the converter simultaneously with low switching frequency and low capacitor voltage ripple at every sub-module besides a correct energy balance between arms. In addition, a new method to implement (2N+1) SHE-PWM for MMCs, which is also valid to implement standard SHE-PWM for any MC, is provided. Using this method, different equation systems are not required for every switching pattern. In this way, this technique provides simultaneously both the switching patterns and the firing angles which solve the SHE problem, simplifying the searching task. Simulation results which have been obtained from a MMC with 5 sub-modules at every arm, have validated the novel proposed circulating current control. Furthermore, the spectrum of the simulated line to line voltage waveform has proved the correct performance of the proposed (2N+1) SHE-PWM implementation method. Several sets of angles have been provided throughout the ma range, where 17 harmonics have been controlled.

Design of a frequency adaptative control for a grid-connected single-phase voltage source inverter

The performance of modular multilevel converters (MMCs) in medium-voltage applications, where the number of required submodules is not high, can be improved utilizing low switching frequency modulations such as (2N+1) selective harmonic elimination-pulse width modulation (SHE-PWM), which provides tight control of lower order harmonics and low switching losses. This paper proposes a calculation method, which is based on a novel formulation, to solve the SHE-PWM problem. In particular, MMCs with (2N+1) phase output voltage levels are considered, obtaining a (2N+1) SHE-PWM waveform. This method utilizes a unique system of equations that is valid for any possible waveform. Therefore, it is able to calculate simultaneously, without predefined waveforms, both the switching patterns and the associated firing angles that solve the (2N+1) SHE-PWM problem. Consequently, the search process is simplified and optimized. Furthermore, this paper also proposes a circulating current control technique, which can be applied along with (2N+1) SHE-PWM without disturbing the phase output voltage. Simulation results and experimental tests obtained with a single-phase laboratory prototype prove the validity of the novel (2N+1) SHE-PWM implementation method and the proposed circulating current control technique.

Matrix converter fed small wind turbine farms: Optimization of the simulation process

Many digital circuit’s functionality is strongly dependant on high speed data exchange between data source and sink elements. In order to alleviate the main processor’s work, it is usually interesting to isolate high speed data exchange from all other control tasks. A generic architecture, based on configurable cores, has been achieved for slave circuits controlled by an external host and with extensive data exchange requirements. Design reuse has been improved by means of a software application that helps on configuration and simulation tasks. Two applications implemented on FPGA technology are presented to validate the proposed architecture.