Eider Robles

Voltage-Balance Compensator for a Carrier-Based Modulation in the Neutral-Point-Clamped Converter

This paper presents an optimal voltage-balancing compensator for a specific modulation technique applied to a neutral-point-clamped converter. The technique uses two modulation signals per phase, and it is called double-signal pulsewidth modulation. It completely eliminates low-frequency oscillations in the neutral-point voltage. However, it does not provide natural voltage balancing; therefore, a compensation loop is required. The proposed control generates a feedback compensation signal that correctly modifies the three-phase modulation signals. The optimal compensation signal is calculated by a dynamic limiter according to the intrinsic limitations of the system related to the variability range of the modulation signals. It significantly improves the voltage balancing under all operating conditions of the converter. In addition, this compensation strategy does not increase the switching frequencies of the power devices. The algorithm is tested and verified using both simulation and experimentation.

A Comprehensive Study of a Hybrid Modulation Technique for the Neutral-Point-Clamped Converter

This paper presents a hybrid modulation technique for the three-level neutral-point-clamped converter. A modulation strategy, based on two modulation signals per phase, was presented previously. This strategy completely removes the low-frequency voltage oscillations that appear at the neutral point (NP) in some operation conditions. However, it also has a major drawback: it significantly increases the switching losses of the converter. The proposal in this paper combines such a modulation strategy with sinusoidal pulsewidth modulation (SPWM). The main characteristic of this hybrid modulation is the reduction in switching losses at the cost of some low-frequency voltage oscillations at the NP. The amplitude of these oscillations can be controlled by varying the combination of the two strategies. The performance of the hybrid modulation is analyzed and compared with the original strategies. Power losses and oscillation amplitudes on the dc-link capacitors are evaluated. Experimental results show how the hybrid modulation performs by balancing the dc-link capacitors.

Three-Level Converter Topologies With Switch Breakdown Fault-Tolerance Capability

This paper presents some modified topologies of the neutral-point-clamped converter. In all of them, the main change consists of adding a fourth leg, which is based on the flying-capacitor converter structure. The aim of this additional leg is to provide the converter with fault tolerance. Furthermore, during normal operation mode, this leg is able to provide a stiff neutral voltage. Consequently, the low-frequency voltage oscillations that appear at the neutral point of the standard three-level topology in some operating conditions no longer exist. As a result, the modulation strategy of the three main legs of the converter does not have to take care of voltage balance, and it can be designed to either achieve optimal output voltage spectra or improve the efficiency of the converter. Simulation and experimental results are presented to show the viability of this approach both under normal operation mode and in the event of faults.

Variable-Frequency Grid-Sequence Detector Based on a Quasi-Ideal Low-Pass Filter Stage and a Phase-Locked Loop

This paper proposes a filtered-sequence phase-locked loop (FSPLL) structure for detection of the positive sequence in three-phase systems. The structure includes the use of the Park transformation and moving average filters (MAF). Performance of the MAF is mathematically analyzed and represented in Bode diagrams. The analysis allows a proper selection of the window width of the optimal filter for its application in the dq transformed variables. The proposed detector structure allows fast detection of the grid voltage positive sequence (within one grid voltage cycle). The MAF eliminates completely any oscillation multiple of the frequency for which it is designed; thus, this algorithm is not affected by the presence of imbalances or harmonics in the electrical grid. Furthermore, the PLL includes a simple-frequency detector that makes frequency adaptive the frequency depending blocks. This guarantees the proper operation of the FSPLL under large frequency changes. The performance of the entire PLL-based detector is verified through simulation and experiment. It shows very good performance under several extreme grid voltage conditions.

Performance Evaluation of Fault-Tolerant Neutral-Point-Clamped Converters

This paper presents a study of the fault tolerance capacity of a neutral-point-clamped converter. Different faults in power semiconductors are considered, and the available postfault states of the converter are shown. In regard of the operation limits, two possible solutions are presented. In these solutions, adding a reduced number of additional components, the behavior of the converter when a switch fails improves considerably. Furthermore, an analysis of the neutral-point voltage balancing conditions after a fault and reconfiguration of the system is also evaluated. Experimental results that prove the correct operation of the proposed topologies are shown.

Frequency-Adaptive Stationary-Reference-Frame Grid Voltage Sequence Detector for Distributed Generation Systems

This paper proposes a stationary-frame sequence detector (SFSD) structure for determining the positive sequence in three-phase systems. The structure includes the use of the Clarke transformation and moving average filters (MAFs). The positive-sequence phase angle can be obtained from the alpha-beta components; however, such a detection becomes inaccurate if the grid voltages are unbalanced and/or distorted. The MAF is used to filter the nonideal components. Performance of the MAF is analyzed mathematically for a proper selection of the window width of the optimal filter in this application. The time delay introduced by MAFs is constant and known; hence, this may be compensated. The proposed detector structure allows fast detection of the grid voltage positive sequence (within one grid voltage cycle). The MAF completely eliminates any oscillation multiple of the frequency for which it is designed; thus, this algorithm can overcome the presence of imbalances or harmonics in the electrical grid. Furthermore, it includes a simple frequency estimator that makes the SFSD frequency adaptive and is capable of operating under large frequency changes. The entire SFSD is verified through simulation and experiment, showing very good performance even under several extreme grid voltage conditions.

Fault-Tolerant Neutral-Point-Clamped Converter Solutions Based on Including a Fourth Resonant Leg

This paper presents a new three-level topology based on the neutral-point (NP)-clamped converter. An additional leg is added to the basic topology. The main purpose of this leg is to provide the converter with fault-tolerant capabilities. In addition, during normal operation mode, the fourth leg can be used to balance the NP voltage. In this way, the low-frequency voltage oscillations that appear in the NP under some operating conditions are cancelled out effectively. As a result, the modulation strategy of the three main legs of the converter does not have to take care of the voltage balance and can focus on other aspects such as, for instance, minimizing the switching losses of the converter. However, the inclusion of the fourth leg produces some additional losses. A resonant topology is proposed to minimize the switching losses of this leg. Three different fault-tolerant solutions based on the fourth-leg topology are presented. A comparison of these topologies showing their respective advantages and drawbacks is made. Experimental results are presented to show the viability of this approach.

Three-Leg Fault-Tolerant Neutral-Point-Clamped Converter

This paper presents a study of the fault tolerance capacity of a neutral-point-clamped (NPC) converter. Furthermore, two possible solutions are presented. In these solutions, adding a reduced number of additional components, the behavior of the converter when a switch fails improves considerably. Simulations results that prove the correct operation of the proposed topologies are shown.

Soft-Switching Topology for a Fault-Tolerant Neutral-Point-Clamped Converter

This paper presents a new three-level topology based on the neutral-point-clamped converter. The new topology includes a fourth leg that provides fault tolerance to the converter. Furthermore, during normal operation mode, this leg is able to provide a stiff neutral voltage. Consequently, the low- frequency voltage oscillations that appear in the neutral point of the standard three-level topology for some operation conditions no longer exist. As a result, the modulation strategy of the three main legs of the converter does not have to take care of voltage balance, and it can be design to improve the efficiency of the converter. On the other hand, the addition of a fourth leg to the converter produces additional losses. However, in order to eliminate switching losses of this leg, all the power devices commutate under zero-current or zero-voltage transitions. Some simulation results are presented to show viability of this approach under both, normal operation mode and fault event.

Grid synchronization method based on a quasi-ideal low-pass filter stage and a phase-locked loop

This paper proposes a new phase-locked loop (PLL) scheme for detection of the positive sequence in three-phase systems. The scheme includes the use of the Park transformation and moving average filters (MAF). Performance of the MAF is mathematically analyzed and represented in Bode diagrams. The analysis allows proper selection of the optimal filterpsilas window width for its application in d-q transformed variables. The proposed detector scheme allows fast detection of the grid voltage positive sequence (within one grid voltage cycle). The MAF completely eliminates any oscillation multiple of the frequency for what it is designed. Thus, this algorithm is not affected by the presence of imbalances or harmonics in the electrical grid. Furthermore, although it is designed to operate under constant frequency, it can also operate properly well in the presence of small grid frequency variations. Performance of the entire PLL-based detector is verified through simulation and experiment. It shows very good performance under several extreme grid voltage conditions.