Antonio J. Ginés

A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects

Current system-on-chip (SoC) designs incorporate an increasing number of mixed-signal components. Design reuse techniques have proved successful for digital design but these rules are difficult to transfer to mixed-signal design. A top-down methodology is missing but the low level of abstraction in designs makes system integration and verification a very difficult, tedious and complex task. This paper presents a contribution to mixed-signal design reuse where a design methodology is proposed based on modular and parametric behavioural components. They support a design process where non-ideal effects can be incorporated in an incremental way, allowing easy architectural selection and accurate simulations. A working example is used through the paper to highlight and validate the applicability of the methodology.

Digital background calibration technique for pipeline ADCs with multi-bit stages

This paper presents a technique for background calibration of pipeline ADCs with multi-bit stages, based on an adaptive approach. Different implementations of the LMS algorithm have been studied, concluding that the traditional SS-LMS (sign-sign LMS) algorithm has inherent convergence problems in high accuracy ADCs that can be solved considering an SD-LMS (sign-data LMS) implementation.

Background Digital Calibration of Comparator Offsets in Pipeline ADCs

This brief presents a low-cost digital technique for background calibration of comparator offsets in pipeline analog-to-digital converters (ADCs). Thanks to calibration, comparator offset errors above half the stage least-significant bit margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and allowing their optimization for low-power high-speed applications and low input capacitance. The technique also makes it possible to relax design requirements of stage amplifiers within the pipeline queue, since output swing and driving capability are significantly lower. In this brief, the proposal is validated using realistic hardware-behavioral models.

Digital background gain error correction in pipeline ADCs

This paper presents a new digital technique for background calibration of gain errors in pipeline ADCs. The proposed algorithm estimates and corrects both the MDAC gain error of the stage under calibration and the global gain error associated to the uncalibrated stages without interruption of the conversion and without reduction of the dynamic rate. It is based on the use of a stage with two input-output characteristics, depending on the value of a digital noise signal.

Improved Background Algorithms for Pipeline ADC Full Calibration

A unified description of the correlation-based techniques for background calibration of pipeline ADCs using additive modulation at the MDAC output is presented in this paper. Two different algorithms for full calibration of this kind of converter which at least a factor 2 improvement in convergence speed, memory resources and stage output swing requirements over previous MDAC modulation approaches are also proposed.

Power optimization of CMOS programmable gain amplifiers with high dynamic range and common-mode feed-forward circuit

A 1.2V 1.95mW low-power Programmable Gain Amplifier (PGA) with high-input range is proposed and implemented in a 90nm CMOS process. The PGA is formed by three stages with a bandwidth of 20MHz for a 2pF capacitive load. Gain is in the range between 0 and 72dB in steps of 6dB. The stage core consists in a differential super-source follower (SSF) with programmable resistive degeneration. Each stage uses a front-end capacitive decoupling network which allows a robust selection of the operating point for improving linearity and reducing power. Further power saving is achieved with a common-mode feed-forward circuit (CMFFC), based on a simple current conveyor. The total PGA area is 165×33µm2 in a 90nm CMOS process. Post-layout simulations at maximum gain show a THD of −57dB and −42dB for output amplitudes of 0.6Vpp and 1.2Vpp, respectively. Input referred noise is just 10.2nVrms/√Hz from 1MHz to 4MHz.

INL systematic reduced-test technique for Pipeline ADCs

This paper presents a procedure to implement a high efficient test of the Integral Non-linearity (INL) of Pipeline ADCs using an extremely reduced set of test input amplitude levels (one order of magnitude lower than the total number of codes in the ADC). For a given architecture, the method provides the way to determine these levels to robustly capture the nonlinearity information. The location of each test level within the input range has low sensitivity to the internal ADC noise, and therefore, they are a good basis to continuously monitor the impact of process, aging and environment conditions variations (PVT) on the non-linearity, as well as miscalibration and possible failures in both foreground and background applications. The proposed method has been validated by realistic behavioral models in several examples.

A survey on digital background calibration of ADCs

In this paper, a general description of digital ADC calibration approaches in current state-of-the-art is presented, with particular emphasis in Pipeline converters. The study performs a classification of the existing techniques considering two basic aspects: a) the principle of operation and the particular errors which can be compensated after calibration, b) the process from which a measurement of the errors, and therefore the calibrated output code, is obtained. Attention will be paid to those approaches applied in background mode and hence not requiring the interruption of the normal ADC operation.

Low-jitter differential clock driver circuits for high-performance high-resolution ADCs

High-performance analog to digital converters (ADCs) require low-jitter clocks in order to obtain high resolutions (above 12 effective bits) at high-speed operation frequencies (input frequency higher than 80MHz). In these ultra-low-jitter applications, clock driver circuits consider multi-stage architectures usually comprised by a front-end differential amplifier, and a differential-to-single (D2S) conversion in voltage mode, followed by an output digital buffer. This paper proposes an alternative to perform the D2S operation in current mode as a way to optimize the trade-offs between power consumption and output jitter. Different clock driver circuit topologies with ultra-low-jitter specifications (<; 200fs) are introduced and compared in a 0.18μm commercial CMOS process.

Sigma-delta testability for pipeline A/D converters

Pipeline Analog to Digital Converters (ADCs) are widely used in applications that require medium to high resolution at high acquisition speed. Despite of their quite simple working principles, they usually form rather complex mixed-signal blocks, particularly if digital correction and calibration are considered. As a result, pipeline converters are difficult to test and diagnose. In this paper, we propose to reconfigure the internal Multiplying DACs (MDACs) that perform residue amplifications as integrators, each one with an analog and a digital input. In this way, we can reuse consecutive pipeline stages to form ΣΔ modulators, with very reduced area overhead. We thus get an on-chip DC (low-frequency) probe with a digital 1-bit output that does not require any extra pin. In addition, digital test techniques developed for ΣΔ modulators may be used to enhance the diagnosing capabilities. An industrial 1.8V 15-bit 100Msps pipeline ADC that had previously been fully validated in a 0.18μm CMOS process is used as a case of study for the introduction of the DfT modifications.