Soumya Chandramouli

Realization of multigigabit channel equalization and crosstalk cancellation integrated circuits

In this paper, we present integrated circuit solutions that enable high-speed data transmission over legacy systems such as short reach optics and electrical backplanes. These circuits compensate for the most critical signal impairments, intersymbol interference and crosstalk. The finite impulse response (FIR) filter is the cornerstone of our architecture, and in this study we present 5- and 10-Gsym/s FIR filters in 2-/spl mu/m GaAs HBTs and 0.18-/spl mu/m CMOS, respectively. The GaAs FIR filter is used in conjunction with spectrally efficient four-level pulse-amplitude modulation to demonstrate 10-Gb/s data throughput over 150 m of 500 MHz/spl middot/km multimode fiber. The same filter is also used to demonstrate equalization and crosstalk cancellation at 5 Gb/s on legacy backplane. The crosstalk canceller improves the bit error rate by five orders of magnitude. Furthermore, our CMOS FIR filter is tested and demonstrates backplane channel equalization at 10 Gb/s. Finally, building blocks for crosstalk cancellation at 10 Gb/s are implemented in a 0.18-/spl mu/m CMOS process. These circuits will enable 10-Gb/s data rates on legacy systems.

Equalization and near-end crosstalk (NEXT) noise cancellation for 20-Gb/s 4-PAM backplane serial I/O interconnections

Limitations in current backplane environments impede high-speed data transmission above 5 Gb/s. A system architecture to extend the transmission capacities of legacy backplanes is proposed. The incentives for using a four-level pulse amplitude modulation (4-PAM) scheme are also presented. The architecture is built from feed-forward equalizer and tunable filter elements for near-end crosstalk noise cancellation. Each of the circuits is implemented in a standard 0.18-/spl mu/m CMOS process. The building blocks of the architecture, which include an LC ladder, a modified Gilbert-cell multiplier with improved headroom, and a tunable active high-pass filter are described in detail. Results of the architecture are shown demonstrating 20-Gb/s 4-PAM signal transmission.

0.18-/spl mu/m CMOS equalization techniques for 10-Gb/s fiber optical communication links

Limitations in data transmission caused by modal dispersion in fiber-optic links can be significantly improved using equalization techniques. In this paper, two different equalizer implementation approaches are proposed to extend the transmission capacities of existing fiber-optic links. The building blocks of the equalizer including a multiplier cell, a delay line, and an output buffer stage are fully integrated on a 0.18-/spl mu/m CMOS process. For the continuous-time tap-delay implementation, a passive LC delay line and an active inductance peaking delay line are compared for performance against process variation, as well as power consumption. In addition, a delay-locked loop is proposed to counter delay variations caused by changes in the process corner. A 10-Gb/s nonreturn-to-zero signal is received after transmission through a 500-m multimode-fiber channel, and the signal impairment due to the differential modal delay is successfully compensated using both feed-forward equalizers.

A 10-Gb/s Reconfigurable CMOS Equalizer Employing a Transition Detector-Based Output Monitoring Technique for Band-Limited Serial Links

Limitations in data transmission caused by band limitation in broadband communication links can be improved significantly by using equalization techniques. In this paper, a reconfigurable feed-forward equalizer employing a transition detector (TD)-based calibration technique that provides a universal channel compensation solution is presented. Moreover, the newly proposed TD-based calibration technique monitors the channel output for further adjustments over time in order to provide optimum compensation in performance. The reconfigurable equalizer is implemented in a 0.18-mum CMOS technology. The prototype successfully demonstrates the feasibility of the TD-based calibration technique for output monitoring

10-Gb/s Optical Fiber Transmission Using a Fully Analog Electronic Dispersion Compensator (EDC) With Unclocked Decision-Feedback Equalization

A 10-Gb/s data transmission over optical fiber is limited in reach due to optical dispersion phenomena that results in inter-symbol interference. Electronic dispersion compensators employing linear and nonlinear equalization techniques are a compact, cost-effective, and adaptive alternative to optical dispersion compensating techniques and devices that are often bulky, expensive, and not adaptive. The decision-feedback equalizer (DFE) is a type of nonlinear equalizer that can effectively compensate for the nonlinear dispersion effects exhibited by fiber channels. However, at multigigabit/second data rates, the implementation of the DFE is challenged by the first feedback-loop latency requirements and process technology speed limitations. This study demonstrates a novel analog approach and circuit architecture to perform decision-feedback equalization at multigigabit/second data rates. The analog decision-feedback equalizer (ADFE) consists of a four-tap linear analog feed-forward filter and a one-tap nonlinear analog feedback filter and is implemented in a 0.18-mum CMOS process. The ADFE is completely differential and a broadband single-differential converter is designed for the ADFE front-end to interface with the single-ended output of a photodetector. The circuit is unclocked and uses current-mode logic techniques. The ADFE is used to extend the transmission distance of multimode fiber at 10-Gb/s to 300 in and of single-mode fiber to 120 km.

A 0.18/spl mu/m CMOS equalizer with an improved multiplier for 4-PAM/20Gbps throughput over 20 inch FR-4 backplane channels

In this paper, we present a 20 Gbps throughput PAM-4 analog feed forward equalizer with a newly proposed multiplier cell. The conventional Gilbert-cell multiplier is modified to achieve enough voltage headroom for 0.18/spl mu/m standard CMOS process while maintaining high-speed characteristics. Pulse amplitude modulation (PAM)-4 is adopted to increase the overall data throughput over bandwidth limited channel. For the tap delay line implementation, a passive L-C ladder topology is used, which enables fractional symbol tap spacing while maintaining the bandwidth required for 20 Gbps PAM-4 signal. The overall architecture is implemented using 0.18 /spl mu/m, standard CMOS process with 1.8V supply voltage. The 20 Gbps PAM-4 signal is received through the backplane channel, and the signal impairment is successfully compensated through the fabricated FFE.

An Electronic Dispersion Compensator (EDC) With an Analog Eye-Opening Monitor (EOM) for 1.25-Gb/s Gigabit Passive Optical Network (GPON) Upstream Links

Today, network systems require higher bandwidth for applications such as fiber-to-the-home communications. Gigabit passive optical network (GPON) links using a Fabry-Perot laser are attractive solutions for this high-speed network. However, due to the mode partition noise and fiber dispersion, GPON systems suffer from inter-symbol interference (ISI). In this paper, we present an electronic dispersion compensator (EDC) that will improve a 1.25-Gb/s experimental GPON link. The experimental GPON link is simulated and measured with impairment assessment. An analog eye-opening monitor, which captures the quality of the EDC output signal using the tunable delay and the integrator is proposed. The proposed EDC successfully compensates ISI for a given link with a 1.25-Gb/s signal. All circuits are fabricated using a 0.18mum- CMOS process.

A 0.25-um BiCMOS Feed Foward Equalizer Using Active Delay Line for Backplane Communication

In this paper, a BiCMOS equalizer using an active delay line structure for backplane communication is investigated. Equalization is achieved using a finite impulse response (FIR) filter. The filter is implemented using variable gain blocks and delay elements. The variable gain function is implemented using a Gilbert cell topology, modified for high-speed application. The delay line is implemented using active devices. The active delay line consumes less area than a passive L-C delay line, and has improved bandwidth as well as performance over process variation. The equalizer is implemented in a 0.25-mum BiCMOS technology. To the best our knowledge, it is the first BiCMOS equalizer using an active delay line approach.

Fully integrated 0.18/spl mu/m CMOS equalizer with an active inductance peaking delay line for 10Gbps data throughput over 500m multimode fiber

In this paper, we present a fully integrated equalizer for 10Gbps data throughput over multimode fiber. The equalizer uses a newly proposed active delay line approach with an active inductance. The active inductance enables 10Gbps data throughput equalization with an integrated single to differential converter. A buffer stage is also integrated at the output stage to deliver low voltage differential signaling (LVDS) level at the 50-ohm termination. The overall architecture is implemented using a 0.18/spl mu/m, standard CMOS process with a 1.8V supply voltage. The active delay line scheme results in reduced equalizer chip area in comparison to a passive delay line approach. The 10Gbps non return-to-zero (NRZ) signal is received through a 500m multimode fiber channel, and the signal impairment due to the differential mode delay is successfully compensated.

A low additive noise interference canceller for high sensitivity applications

A canceller is designed to suppress undesired interference in an 802.11b WLAN radio from a Bluetooth radiator operating close to it. The design utilizes 0.18 mum CMOS IC technology. The system consists of a core that emulates the interference-coupling channel between the two radios by time domain amplitude and phase alignment, and filtration. This is controlled by an adaptive loop. Using low noise design principles, the canceller core maintains a low output noise power spectral density of -173 dBm/Hz at the center frequency of the WLAN band. The consequent degradation of WLAN receiver sensitivity is 2.7 dB while achieving at least 15 dB of interference suppression. The canceller core dissipates 20 mW of power.