Toshifumi Irisawa

Device Design and Electron Transport Properties of Uniaxially Strained-SOI Tri-Gate nMOSFETs

We propose effective subband engineering for electron mobility enhancement on a (110) surface, utilizing uniaxial tensile strain along (110) direction. This strain causes the re-population of electrons from fourfold valleys to twofold valleys, resulting in high mobility enhancement along the (110) direction. Using this concept, a 2.0x mobility enhancement in uniaxially strained silicon-on-insulator (SOI) trigate nMOSFETs with (110) sidewall channels has been realized. Here, the uniaxial tensile strain is applied by using anisotropic strain relaxation of biaxiallv strained-SOI substrates. It is also found that (110) current (strain) direction is the best for strained trigate nMOSFETs, suggesting that optimum multigate CMOS structures with enhanced mobility of both electrons and holes can be realized on a conventional (001) wafer in the same (110) current flow direction for nMOSFETs and pMOSFETs.

Device quality Sb-based compound semiconductor surface: A comparative study of chemical cleaning

We have studied the surface cleaning of Sb-based compound semiconductors using HF, NH4OH, and HCl cleans and the metal–oxide–semiconductor (MOS) capacitors fabricated subsequently. GaSb, InGaSb, and AlGaSb surfaces are investigated using low-energy radiation from the synchrotron. Capacitance–voltage (C–V) and photoluminescence measurements are carried out on capacitors made with Al2O3 from atomic layer deposition and corroborated with the results from synchrotron spectroscopy. Excellent C–V characteristics with a mid-band-gap interface state density of 3 × 1011/cm2eV are obtained on samples with the HCl clean. This is consistent with the finding that only the HCl acid clean is able to remove the native oxides present on GaSb and InGaSb surfaces, and produce clean and stable surfaces suitable for MOSFET development. Complete removal of AlOx on the AlGaSb surface was not possible using chemical cleaning. Termination of AlGaSb with two monolayers of GaSb is proposed as a solution.

High-Performance Uniaxially Strained SiGe-on-Insulator pMOSFETs Fabricated by Lateral-Strain-Relaxation Technique

Novel uniaxially strained SiGe-on-insulator (SGOI) pMOSFETs with Ge content of 20% have been successfully fabricated by utilizing lateral (uniaxial) strain-relaxation process on globally (biaxially) strained SGOI substrates. Drastic increase of drain current (80%) caused by the change of strain from biaxial to uniaxial and the mobility enhancement of about 100% against the control Si-on-insulator pMOSFETs are observed in SGOI pMOSFET. This high mobility enhancement is maintained in high vertical effective fields as well as in short-channel devices. As a result, significant ION enhancement of 80% is demonstrated in 40-nm gate-length uniaxially strained SGOI pMOSFET

Examination of Additive Mobility Enhancements for Uniaxial Stress Combined with Biaxially Strained Si, Biaxially Strained SiGe and Ge Channel MOSFETs

Uniaxial and biaxial strain additive mobility enhancements and their physical understandings are experimentally examined by applying mechanical stress to high mobility channel materials. As for nMOSFETs, <110> uniaxial and biaxial tensile strain are partially additive in the electron mobility enhancement due to the conduction band warping and resulting effective mass reduction under shear strain. As for pMOSFETs, it is found that an initial compressive biaxial strain is efficient to boost the impact of the shear strain component in the <110> uniaxial strain on hole mobility, demonstrating the effectiveness in combining uniaxial and biaxial stress for strained SiGe channels. The piezoresistance coefficients for (001) Germanium pMOSFETs are also experimentally evaluated for the first time.

On the origin of increase in substrate current and impact ionization efficiency in strained-Si n- and p-MOSFETs

Strain dependence of substrate current and impact ionization efficiency in the strained-Si n- and p-MOSFETs has been systematically investigated with the wide range of strain, by utilizing the universal relationship between the impact ionization efficiency and the electrical field in the pinch-off region. It was found that the impact ionization efficiency increased with increasing strain, leading to the drastic increase of substrate current, and that the strain dependence of impact ionization efficiency was well represented by simply using the strain dependence of the bandgap energy regardless of carrier type. This result strongly suggests that the strain-induced enhancement of impact ionization efficiency is not due to the modification of the carrier transport properties but to the narrowing of the bandgap, and presumably, the resulting decrease in threshold energy for impact ionization. It was also found that the impact ionization efficiency increased with the increase of temperature while its dependence did not exhibit distinct strain dependence. These results are attributable mainly to the temperature dependence of energy distribution function.

Deformation Induced Holes in Ge-Rich SiGe-on-Insulator and Ge-on-Insulator Substrates Fabricated by Ge Condensation Process

Electrical properties of Ge-rich SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) structures fabricated by Ge condensation process have been studied. The SGOI and GOI structures for Ge composition, xGe, larger than 0.4 exhibit p-type conduction. The hole density is found to rapidly increase from 1016 to 1018 cm-3 with an increase in xGe during the Ge condensation and to decrease down to low-1017 cm-3 when xGe reaches unity. Analyses of scanning spreading resistance microscopy have directly revealed that the SGOI and GOI structures are highly conductive along the crosshatched slip bands formed during the condensation, meaning that the holes are induced along the slip bands in SGOI and GOI films. As a result, it is concluded that the hole induced during the Ge condensation is strongly associated with the slip band formation.

Development of high-k dielectric for antimonides and a sub 350°C III–V pMOSFET outperforming Germanium

In<inf>x</inf>Ga<inf>1−x</inf>Sb pMOSFETs with SS of 120mV/decade, I<inf>ON</inf>/I<inf>OFF</inf>>10⁴ and Gm,max of 140/90 mS/mm (L<inf>G</inf>=5µm), fabricated using a self-aligned gate-first process are demonstrated for the first time. Table 2, summarizes the key transistor results. ALD Al<inf>2</inf>O<inf>3</inf> with Dit of 3×10¹¹/cm²eV and strain engineering has enabled a high-mobility In<inf>x</inf>Ga<inf>1−x</inf>Sb pMOSFET an important step toward the implementation of III–V CMOS in future technology nodes.

Uniaxial Stress Engineering for High-Performance Ge NMOSFETs

Ge channel is one of the promising performance boosters for replacing Si channel in future complementary metal-oxide-semiconductor technology. The uniaxial stress technology can further enhance the performance of Ge MOSFETs. In this paper, the uniaxial stress effect on Ge NMOSFETs was experimentally and theoretically investigated. The gate dielectric in the Ge NMOSFETs was fabricated by using the novel radical oxidation technique. The high quality of the gate dielectric allowed high vertical field mobility measurements. By applying mechanical uniaxial stress on the fabricated Ge NMOSFETs, the mobility enhancement was experimentally obtained. The physical mechanism of mobility enhancement under such strain indicates that the device performance of Ge NMOSFETs in the ballistic transport regime can achieve as much as 48% drive current gain beyond the 15 nm technology node.

Electron Transport Properties of Ultrathin-body and Tri-gate SOI nMOSFETs with Biaxial and Uniaxial Strain

Electron transport properties in biaxially strained UTB MOSFETs and uniaxially strained tri-gate MOSFETs are experimentally investigated. It is found that the strain is still effective even in UTB regime and the mobility enhancement of 1.4 against control thick (20 nm) SOI is preserved in devices with TSoi = 2.4 nm. We also demonstrate 2.0x mobility enhancement in tri-gate nMOSFETs with uniaxial <110> tensile strain that is favored not only on (100) but also on (110) sidewall

Performance enhancement of partially- and fully-depleted strained-SOI MOSFETs and characterization of strained-Si device parameters

This paper demonstrates the successful fabrication of strained-SOI MOSFETs using SiGe on insulator (SGOI) substrates. 200mm SGOI wafer with Ge content of 30% is fabricated by Ge condensation technique. The performance enhancement over 14% is obtained in gate length of 70 nm. Furthermore, fully-depleted strained-SOI MOSFETs with back gate is demonstrated. Thin strained-Si layer can suppress the abnormal off leakage current due to the enhancement impurity diffusion.