Seung-Moon Yoo

A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth

This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V/sub cc/=2.0 V and 25/spl deg/C. The chip employs (1) a merged multibank architecture to minimize die area; (2) an extended small swing read operation and a single I/O line driving write scheme to reduce power consumption; (3) a self-strobing I/O schemes to achieve high bandwidth with low power dissipation; and (4) a block redundancy scheme with increased flexibility. The nonstitched chip with an area of 652 mm/sup 2/ has been fabricated using 0.16 /spl mu/m four-poly, four-metal CMOS process technology.

Variable V/sub CC/ design techniques for battery-operated DRAMs

Wide-voltage-range DRAMs with extended data retention are desirable for battery-operated or portable computers and consumer devices. The techniques required to obtain wide operation, functionality, and performance of standard DRAMs from 1.8 V (two NiCd or alkaline batteries) to 3.6 V (upper end of LVTTL standard) are described. Specific techniques shown are: (1) a low-power and low-voltage reference generator for detecting V/sub CC/ level; (2) compensation of DC generators, V/sub BB/ and V/sub PP/, for obtaining high speed at reduced voltages; (3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and (4) a programmable V/sub CC/ variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16 M DRAM (2 M*8) by simulation. >

Low-voltage, high-speed circuit designs for gigabit DRAMs

This paper describes several new circuit design techniques for low V/sub CC/ regions: 1) a charge-amplifying boosted sensing (CABS) scheme which amplifies the sensing voltage difference (/spl Delta/V/sub BL/) as well as the V/sub GS/ margin by boosting the sensing node voltage with a voltage dependent boosting capacitor and 2) an I/O current sense amplifier with a high gain using a cross-coupled current mirror control scheme and reduced temperature sensitivity using a simple temperature-compensation scheme. An experimental 16 Mb DRAM chip with the 0.18-/spl mu/m twin-well, triple-metal CMOS process has been fabricated, and an access time from the row address strobe (t/sub RAC/) of 28 ns at V/sub cc/=1.5 V and T=25/spl deg/C has been obtained.

A 32-bank 1 Gb DRAM with 1 GB/s bandwidth

This 32-bank 1 Gb DRAM features: (1) a merged bank architecture (MBA) that results in only 3% die area penalty for 32-bank operation; (2) a source-synchronous I/O interface (SSI) that achieves 1 GB/s bandwidth with low power consumption; (3) flexible block redundancy that allows freedom of repair to anywhere within each half-Gb array; and (4) extended small swing read and single-I/O line driving write which result in 30% power reduction. The DRAM chip is implemented in a 0.16 /spl mu/m twin-well CMOS process.

Low voltage high speed circuit designs for giga-bit DRAMs

An experimental 16 Mb DRAM for giga scale densities with a charge-amplifying boosted sensing (CABS) scheme and a new I/O large gain current sense amplifier using a cross-coupled current mirror control scheme achieves a t/sub RAC/ of 28 ns and an average operating current of 22 mA at V/sub CC/=1.5 V, t/sub RC/=70 ns, T=25/spl deg/C. This chip has been fabricated using a 0.18 /spl mu/m twin-well CMOS process with KrF lithography having transistor channel lengths of 0.32(n)/0.40(p)/spl mu/m and low resistance TiSi/sub 2/ wordlines.