R. Castro-López

An Integrated Layout-Synthesis Approach for Analog ICs

In analog integrated circuit design, iterations between electrical and physical syntheses to counterbalance layout-induced performance degradations should be avoided as much as possible. One possible solution involves the integration of traditionally separated electrical and physical synthesis phases by including layout-induced effects right into the electrical synthesis phase in what has been called parasitic-aware synthesis. This solution, as such, is not yet complete since there are geometric requirements (minimization of area or fulfillment of certain layout aspect ratio, among others) whose effects on the resulting parasitics are not usually considered during the electrical synthesis. In this paper, a layout-aware solution for analog cells that tackles both geometric and parasitic-aware electrical synthesis is proposed. Several design examples are provided.

A memetic approach to the automatic design of high-performance analog integrated circuits

This article introduces an evolution-based methodology, named memetic single-objective evolutionary algorithm (MSOEA), for automated sizing of high-performance analog integrated circuits. Memetic algorithms may achieve higher global and local search ability by properly combining operators from different standard evolutionary algorithms. By integrating operators from the differential evolution algorithm, from the real-coded genetic algorithm, operators inspired by the simulated annealing algorithm, and a set of constraint handling techniques, MSOEA specializes in handling analog circuit design problems with numerous and tight design constraints. The method has been tested through the sizing of several analog circuits. The results show that design specifications are met and objective functions are highly optimized. Comparisons with available methods like genetic algorithm and differential evolution in conjunction with static penalty functions, as well as with intelligent selection-based differential evolution, are also carried out, showing that the proposed algorithm has important advantages in terms of constraint handling ability and optimization quality.

Analog layout synthesis: recent advances in topological approaches

This paper gives an overview of some recent advances in topological approaches to analog layout synthesis and in layout-aware analog sizing. The core issue in these approaches is the modeling of layout constraints for an efficient exploration process. This includes fast checking of constraint compliance, reducing the search space, and quickly relating topological encodings to placements. Sequence-pairs, B*-trees, circuit hierarchy and layout templates are described as advantageous means to tackle these tasks.

Adaptive CMOS analog circuits for 4G mobile terminals-Review and state-of-the-art survey

The fourth-generation (4G) of cellular terminals will integrate the services provided by previous generations second-generation/third-generation (2G/3G) with other applications like global positioning system (GPS), digital video broadcasting (DVB) and wireless networks, covering metropolitan (IEEE 802.16), local (IEEE 802.11) and personal (IEEE 802.15) areas. This new generation of hand-held wireless devices, also named always-best-connected systems, will require low-power and low-cost multi-standard chips, capable of operating over different co-existing communication protocols, signal conditions, battery status, etc. Moreover, the efficient implementation of these chipsets will demand for reconfigurable radio frequency (RF) and mixed-signal circuits that can adapt to the large number of specifications with minimum power dissipation at the lowest cost. Nanometer CMOS processes are expected to be the base technologies to develop 4G systems, assuring mass production at low cost through increased integration levels and extensive use of digital signal processing. However, the integration in standard CMOS of increasingly complex analog/RF parts imposes a number of challenges and trade-offs that make their design critical. These challenges are addressed in this paper through a comprehensive revision of the state-of-the-art on transceiver architectures, building blocks and design trade-offs of reconfigurable and adaptive CMOS RF and mixed-signal circuits for emerging 4G systems.

Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors

In this paper, a new methodology for the automated generation of the optimal performance trade-offs of integrated inductors is presented. The methodology combines a multiobjective optimization algorithm with electromagnetic simulation to get highly accurate results. A set of sized inductors is obtained showing the best performance trade-offs for a given technology. Unlike reported approaches for inductor synthesis, performance trade-offs are generated offline, i.e., before any specific inductance or quality factor are required. The tight efficiency versus accuracy trade-off of existing approaches is, in this way, avoided and performance evaluation via electromagnetic simulation becomes affordable.

Analog/RF and Mixed-Signal Circuit Systematic Design

Despite the fact that in the digital domain, designers can take full benefits of IPs and design automation tools to synthesize and design very complex systems, the analog designers task is still considered as a handcraft, cumbersome and very time consuming process. Thus, tremendous efforts are being deployed to develop new design methodologies in the analog/RF and mixed-signal domains. This book collects 16 state-of-the-art contributions devoted to the topic of systematic design of analog, RF and mixed signal circuits. Divided in the two parts Methodologies and Techniques recent theories, synthesis techniques and design methodologies, as well as new sizing approaches in the field of robust analog and mixed signal design automation are presented for researchers and R/D engineers.

Applications of evolutionary computation techniques to analog, mixed-signal and RF circuit design - an overview

This paper reviews the application of evolutionary computation techniques to analog, mixed-signal and radio-frequency design problems. Design needs, limitations of existing approaches and open challenges are pointed out.

Generation of Technology-Independent Retargetable Analog Blocks

This paper introduces a complete methodology for retargeting of analog cells to different sets of specifications. This methodology is technology-independent, thus allowing the migration, from one technology to another, of the circuit under retargeting. Careful integration of the device sizing and layout generation tasks via the incorporation of layout constraints during the sizing process allows to generate fully functional designs in a few minutes. The methodology is illustrated via the retargeting of a fully-differential Miller-compensated two-stage operational amplifier for a new set of specifications and two different technological processes.

Stopping criteria in evolutionary algorithms for multi-objective performance optimization of integrated inductors

In this paper, the application of multi-objective evolutionary algorithms to the evaluation of performance trade-offs of planar inductors, an almost ubiquitous device in radio-frequency microelectronics, is studied. The absence of appropriate stopping criteria in most evolutionary algorithms reveals to be critical in this application. A new stopping criterion based on monitoring a set of performance metrics that account for convergence and diversity is proposed and demonstrated with practical radio-frequency circuit design problems.

Physical vs. surrogate models of passive RF devices

The accuracy of high-frequency models of passive RF devices, e.g., inductors or transformers, presents one of the most challenging problems for RF integrated circuits. Accuracy limitations lead RF designers to time-consuming iterations with electromagnetic simulators. This paper will explore and compare two advanced modeling techniques. The first one is based on the segmented model approach, in which each device segment is characterized with a lumped element model. The second technique is based on the generation of surrogate models from the electromagnetic simulation of a set of device samples. Different modeling strategies (frequency separation, filtering according to self-resonance frequency, etc.) will be considered. Efficiency and accuracy of both, physical and surrogate, modeling techniques will be compared using a Si process technology.