Elliot John Smith

Correlation between the macroscopic ferroelectric material properties of Si:HfO2 and the statistics of 28 nm FeFET memory arrays

ABSTRACT With the discovery of ferroelectric hafnium oxide (FE-HfO2), the ferroelectric field effect transistor (FeFET), a long-term contender for non-volatile data storage, has finally managed to scale to the 2× nm technology node. Here for the first time, we correlate the thickness dependent ferroelectric properties of Si:HfO2 with the memory characteristics of small (56 bit) FeFET arrays. First, an electrical and structural analysis of metal-ferroelectric-metal capacitors is given. Even though possessing room-temperature deposited top electrodes, TiN / Si:HfO2 (20 nm) / TiN capacitors are showing deteriorated polarization characteristics as compared to their 10 nm Si:HfO2 counterparts. This could be attributed to an increased monoclinic phase fraction, as indicated by small-signal capacitance voltage and grazing incidence X-ray diffraction measurements. Identical Si:HfO2 thin films with thicknesses of 10 nm and 20 nm respectively, were utilized in a 28 nm high-k metal-gate CMOS flow to form small FeFET memory arrays of AND architecture. After extracting the most suitable operating conditions from erase matrix, single cell evaluation was performed by standard VP/3 program and a novel VP/3 positive-source drain erase scheme. Array cells incorporating 10 nm Si:HfO2 films showed a maximum memory window of 1.03 V whereas cells incorporating 20 nm Si:HfO2 films could reach up to 1.57 V. Moreover, in accordance to the basic material properties, the previously observed increased monoclinic phase fraction in 20 nm Si:HfO2 thin films correlate well with a reduced number of functional FeFET cells.

RF-pFET in fully depleted SOI demonstrates 420 GHz F T

We report an experimental pFET with 420GHz fT, which to the best of our knowledge is the highest value reported for a silicon pFET. The transconductance is 1800uS/um. The technology is fully depleted silicon on insulator (FDSOI) with the pFET channel formed by SiGe condensation. This outstanding performance is achieved by a combination of layout and process optimization which minimizes capacitance and maximizes compressive strain on the channel. The technology features a high-k metal gate and short gate length (20nm drawn) in addition to the SiGe channel for high mobility.