En-Hsiang Yeh
TSMC
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Publication
Featured researches published by En-Hsiang Yeh.
international electron devices meeting | 2012
Christianto Chih-Ching Liu; Shuo-Mao Chen; Feng-Wei Kuo; Huan-Neng Chen; En-Hsiang Yeh; Cheng-chieh Hsieh; Li-Hsien Huang; Ming-Yen Chiu; John Yeh; Tsung-Shu Lin; Tzu-Jin Yeh; Shang-Yun Hou; Jui-Pin Hung; Jing-Cheng Lin; Chewn-Pu Jou; Chuei-Tang Wang; Shin-Puu Jeng; Douglas Yu
Integrated fan-out wafer-level packaging (InFO-WLP) technology with state-of-the-art inductors (quality factor of 42 and self-resonance frequency of 16 GHz) has been demonstrated for heterogeneous integration of digital and radio frequency (RF) systems. InFO-WLP promises superior form factor, pin count, and thermal performance to existing flip-chip ball grid array (FC-BGA) packages. In addition, InFO-WLPs high Q inductors can enhance electrical performance and lower power consumption in RF circuit applications.
international electron devices meeting | 2013
Chung-Hao Tsai; Jeng-Shien Hsieh; Monsen Liu; En-Hsiang Yeh; Hsu-Hsien Chen; Ching-Wen Hsiao; Chen-Shien Chen; Chung-Shi Liu; Mirng-Ji Lii; Chuei-Tang Wang; Doug C. H. Yu
Array antenna integrated with RF chip using InFO-WLP technology is proposed for millimeter wave system applications. Aperture-coupled patch antenna is designed on the fan-out molding compound (MC). The performance of single-element antenna is evaluated first and proved to have 5 dBi of gain. Meanwhile, the interconnect from chip to antenna feeding line is demonstrated to only have 0.7 dB loss, which can save 19 % PA output power compared with that of flip-chip package. Finally, the system performance of 4 × 4 antenna array integrated with RF chip on the InFO structure shows 14.7 dBi of array gain in a small form factor of 10 × 10 × 0.5 mm3.
international electron devices meeting | 2013
W. C. Lai; H. H. Chuang; C. H. Tsai; En-Hsiang Yeh; C. H. Lin; T. H. Peng; Liang-Ju Yen; W.S. Liao; J. N. Hung; C. C. Sheu; Chung-Yi Yu; C. T. Wang; Kuo-Chung Yee; Doug C. H. Yu
The first publication on fabrication of a 300 mm size, 50 μm ultra-thin glass interposer is presented. According to measured data and modeling analysis, merits of on-glass inductors and transmission lines outperform those of on-silicon in Q-factor, power dissipation, and power/signal integrity. Glass interposer is a promising building block technology for future hybrid mixed signal heterogeneous chip integration solution.
ieee international d systems integration conference | 2015
Chuei-Tang Wang; Jeng-Shien Hsieh; Victor C. Y. Chang; En-Hsiang Yeh; Feng-Wei Kuo; Hsu-Hsien Chen; Chih-Hua Chen; Ron Chen; Ying-Ta Lu; Chewn-Pu Jou; Hao-Yi Tsai; C. S. Liu; Doug C. H. Yu
An integration of 28 nm CMOS RF system with 3D solenoidal inductors (3DSI) in integrated fan-out (InFO) wafer level package technology is studied. The 3DSI provides the performance of Q-factor of 51 and isolation of -53 dB. With the 3DSI, the RF system in the InFO technology results in power saving by 58% and noise reduction by 80% in LNA and VCO, respectively, compared with those in RF SoC system. The InFO technology provides a novel solution for RF system integration.
Archive | 2015
Hsu-Hsien Chen; Chih-Hua Chen; En-Hsiang Yeh; Monsen Liu; Chen-Shien Chen
Archive | 2012
Lai Wei Chih; Monsen Liu; En-Hsiang Yeh; Chuei-Tang Wang; Chen-Hua Yu
Archive | 2012
Hsu-Hsien Chen; Chih-Hua Chen; En-Hsiang Yeh; Monsen Liu; Chen-Shien Chen
symposium on vlsi circuits | 2013
W.S. Liao; H.N. Chen; K.K. Yen; En-Hsiang Yeh; Feng-Wei Kuo; T.J. Yeh; F. Kuo; Chewn-Pu Jou; S. Liu; F.L. Hsueh; H.C. Lin; C.N. Peng; M.J. Wang; W.C. Wu; S.P. Hu; Min-Hui Chen; Shang-Yun Hou; S.P. Jeng; Chung-Yi Yu; Kuo-Chung Yee; Doug Yu
Archive | 2016
Monsen Liu; Lai Wei Chih; Chung-Hao Tsai; Jeng-Shien Hsieh; En-Hsiang Yeh; Chuei-Tang Wang
Archive | 2013
Chung-Hao Tsai; En-Hsiang Yeh; Chuei-Tang Wang