Chung-Hao Tsai

Array antenna integrated fan-out wafer level packaging (InFO-WLP) for millimeter wave system applications

Array antenna integrated with RF chip using InFO-WLP technology is proposed for millimeter wave system applications. Aperture-coupled patch antenna is designed on the fan-out molding compound (MC). The performance of single-element antenna is evaluated first and proved to have 5 dBi of gain. Meanwhile, the interconnect from chip to antenna feeding line is demonstrated to only have 0.7 dB loss, which can save 19 % PA output power compared with that of flip-chip package. Finally, the system performance of 4 × 4 antenna array integrated with RF chip on the InFO structure shows 14.7 dBi of array gain in a small form factor of 10 × 10 × 0.5 mm3.

Magnetic thin-film inductors for monolithic integration with CMOS

This paper presents the fabrication, design and electrical performance of magnetic thin-film inductors for monolithic integration with CMOS for DC-DC power conversion. Magnetic core inductors were fabricated using conventional CMOS processes to achieve peak inductance density of 290nH/mm2, quality factor 15 at 150MHz, current density exceeding 11 A/mm2 and coupling coefficient of 0.89 for coupled inductors.

A high-performance, high-density 28nm eDRAM technology with high-K/metal-gate

This paper presents industrys smallest 0.035um2 high performance embedded DRAM cell with cylinder-type Metal-Insulator-Metal (MIM) capacitor and integrated into 28nm High-K Metal Gate (HKMG) logic technology. This eDRAM memory features an HKMG CMOS compatible (low-thermal low-charging process) high-K MIM capacitor with extreme low leakage (<0.1fA/cell). Access transistor with HKMG shows excellent driving capability (>50uA/cell) with <1fA/cell leakage in 28nm cell and <3fA/cell in 20nm cell (0.021um2). We demonstrate first functional silicon success of 28nm eDRAM macro. 600/550 MHz operating frequency is achieved at typical/worse cases.

A manufacturable interposer MIM decoupling capacitor with robust thin high-K dielectric for heterogeneous 3D IC CoWoS wafer level system integration

A reliability proven high-K (HK) metal-insulator-metal (MiM) structure has been verified within the silicon interposer in a chip-on-wafer-on-substrate (CoWoS) packaging for heterogeneous system-level decoupling application. The HK dielectric has an equivalent oxide thickness (EOT) of 20Å, intrinsic TDDB lifetime of 322 years at an operation voltage (V_cc) of 1.8V, and a leakage current (I_LK) below 1 fA/μm² under +/-2V bias at 125°C. The measured unit area capacitance density for the single, 2- and 3-in-series Si-interposer HK-MiM combination is 17.2, 4.3 and 1.9 fF/μm², respectively, with their corresponding I_LK below 0.48, 0.19 and 0.09 fAmp/μm². Process reliability related defect density (D₀) of the interposer HK-MiM is as low as 0.095% cm^-2 as judged by a 10 years lifetime breakdown voltage (V_bd) criterion at V_cc=3.2V. This low D₀ ensures the Si-interposer HK-MiM to be used in a large area over 1056 cm² within the Si interposer. Moreover, the V_bd tolerance of the HK-MiM can be drastically enhanced to be 9.75 and 14.25V, respectively, by 2- and 3-in-series HK-MiM configuration connection. At the package level during all steps of CoWoS processing, no distinguishable process induced damage (PID) and performance degradation (Cap., I_LK & V_bd tailing) were detected. Therefore, this high capacitance, low leakage, large area and reliability-proven Si-interposer decoupling capacitor (DeCAP) within CoWoS greatly enhances the merit of using Si-interposer HK-MiM capacitors for multi-chip system-level integration.

High performance passive devices for millimeter wave system integration on integrated fan-out (InFO) wafer level packaging technology

High performance passive devices for millimeter wave (MMW) system, including inductor, ring resonator, power combiner, coupler, balun, transmission line, and antenna, are first realized using integrated fan-out (InFO) wafer level packaging technology. The inductors has quality factor over 40; the power combiner, coupler, and balun show lower transmission loss than on-chip passives; antenna has the efficiency of over 60%. These devices on InFO enable low noise and power MMW system for mobile communication and IoT applications.

A high density cylinder-type MIM capacitor integrated with advanced 28nm logic High-K/Metal-Gate process for embedded DRAM

A cylinder-type Metal-Insulator-Metal (MIM) capacitor integrated with advanced 28nm logic High-K/Metal-Gate (HKMG) process for embedded DRAM has been developed. The stacked cell capacitor is formed using low temperature high-K dielectrics to achieve sufficient storage capacitance without significantly impacting logic transistors. This paper describes techniques to achieve cylinder-type MIM capacitors capacitance >;10fF/cell and keep the low leakage (<;0.1fA/cell) requirements. The MIM dielectric reliability test passes Time Dependent Dielectric Breakdown (TDDB) lifetime (>;10 years). The test vehicle is composed of 72 macros of 4.5Mb each. We successfully demonstrate fully functional good yield of 28nm eDRAM 324Mb test vehicle with access speed >;330MHz.

Improved trap-related characteristics on SiN x /AlGaN/GaN MISHEMTs with surface treatment

In this paper, the reliable SiNx/AlGaN/GaN MISHEMTs on silicon substrate with improved trap-related characteristics have been well demonstrated. The devices with our proposed treatment method showed less deep-level traps and more Si surface donors at SiNx-AlGaN interface. The trap related device characteristics are also improved by using our optimized treatment method. The devices with proposed treatment method exhibit less current collapse and better positive bias temperature stability of threshold voltage. All the results suggest that the proposed treatment method is very effective to improve the slow-trap related device reliability.

High Performance Chip-Partitioned Millimeter Wave Passive Devices on Smooth and Fine Pitch InFO RDL

High performance millimeter wave passive devices are realized on smooth, fine pitch InFO redistribution layer (RDL). These passive devices are balun, power combiner, coupler, and microstrip line and the electrical performances are measured from 0.1GHz to 67 GHz through VNA. The measurement results show that the transmission loss of on-InFO balun (4.3 dB), the power divider (4.3 dB), and the coupler (4.9 dB) outperforms on-chip one by 2.1 dB, 1 dB, and 0.2 dB, respectively. While the transmission loss of microstrip line (0.34 dB/mm) is better than on-chip one by 0.17 dB/mm at 60 GHz. Furthermore, the parasitic of InFO chip-package interconnection has been investigated and compared to other technologies with and without solder bumps. The parasitic resistance, inductance, and capacitance for InFO interconnection are 75 %, 76 %, and 14 % lower than those for chip-last, face-down technology. Parasitic resistance for InFO RDL is 10 % lower than that for chip-first face-down technology with uneven RDL.

Taper pad design to improve electrical performance of BGAs on wafer level package (WLP)

A taper pad design is proposed to improve signal integrity in the transition from traces on chip site to PCB. Transmission loss of the transition incorporating traces, taper pads, solder balls, and microstrip line is simulated through electromagnetic simulation tool. Compared with the conventional pad design, the proposed pad design has 2 dB of improvement and only 0.9 dB insertion loss at 40 GHz. In addition, its DC/AC parasitic resistance and AC parasitic inductance are extracted and proved to have 85/65 % and 19 % of reduction, respectively, against the conventional pad design. Finally, the design guide of the proposed pad design is presented to enhance the signal integrity of WLP.