Chuei-Tang Wang

High-performance integrated fan-out wafer level packaging (InFO-WLP): Technology and system integration

Integrated fan-out wafer-level packaging (InFO-WLP) technology with state-of-the-art inductors (quality factor of 42 and self-resonance frequency of 16 GHz) has been demonstrated for heterogeneous integration of digital and radio frequency (RF) systems. InFO-WLP promises superior form factor, pin count, and thermal performance to existing flip-chip ball grid array (FC-BGA) packages. In addition, InFO-WLPs high Q inductors can enhance electrical performance and lower power consumption in RF circuit applications.

A leading-edge 0.9µm pixel CMOS image sensor technology with backside illumination: Future challenges for pixel scaling

This paper presents process breakthroughs that enable a BSI 0.9µm pixel formation and its performance. The technology was developed using 300mm bulk silicon starting wafers with the state-of-the-art tool set for BSI sensor processing. This is the first demonstration of 0.9µm BSI pixel with acceptable optical performance. Further improvements are in the area of crosstalk suppression and color performance enhancement for continuous pixel scaling from 0.9µm.

Array antenna integrated fan-out wafer level packaging (InFO-WLP) for millimeter wave system applications

Array antenna integrated with RF chip using InFO-WLP technology is proposed for millimeter wave system applications. Aperture-coupled patch antenna is designed on the fan-out molding compound (MC). The performance of single-element antenna is evaluated first and proved to have 5 dBi of gain. Meanwhile, the interconnect from chip to antenna feeding line is demonstrated to only have 0.7 dB loss, which can save 19 % PA output power compared with that of flip-chip package. Finally, the system performance of 4 × 4 antenna array integrated with RF chip on the InFO structure shows 14.7 dBi of array gain in a small form factor of 10 × 10 × 0.5 mm3.

High performance 300mm backside illumination technology for continuous pixel shrinkage

Backside Illumination (BSI) sensor with excellent optical performance has become the main-stream CMOS image sensor process. This work addressed the key factors and issues for 300mm BSI technology, including wafer distortion, silicon thickness variation, backside junction formation and dielectric film structure, thermal annealing and so on. It is demonstrated that with the optimized key process, a high performance 0.9um BSI pixel with low noise can be fabricated.

Signal and Power Integrity Analysis on Integrated Fan-Out PoP (InFO_PoP) Technology for Next Generation Mobile Applications

A novel integrated fan-out package on package (InFO_PoP) technology for application processor (AP), memory, and PMIC system is developed for next generation high performance mobile applications. For AP and memory system, the InFO_PoP technology can provide better system performance and lower package profile, compared to current flip-chip package on package (FC_PoP) technology. For signal integrity, the eye height of eye diagram for the InFO_PoP is 24% larger than that for the FC_PoP at LPDDR4. For power integrity, the PDN impedance for the InFO_PoP is 84% lower than that for the FC_PoP at high frequency because of thinner dielectric layer between power/ground planes and shorter path from AP pad to PCB. For AP and PMIC system, an advanced power delivery network (PDN) is proposed to minimize the supply voltage variation and transient time using face-to-face interconnection between AP package and partitioned voltage regulators (PVRs) chip from PMIC package. The voltage variation of the InFO_PoP with PVRs system is 43% lower than that of the FC_PoP with PVRs system. Meanwhile, the InFO_PoP with PVRs system exhibits immediate transient response. The transient time of InFO_PoP with PVRs system is 54% less than that of the FC_PoP with PVRs system.

High performance passive devices for millimeter wave system integration on integrated fan-out (InFO) wafer level packaging technology

High performance passive devices for millimeter wave (MMW) system, including inductor, ring resonator, power combiner, coupler, balun, transmission line, and antenna, are first realized using integrated fan-out (InFO) wafer level packaging technology. The inductors has quality factor over 40; the power combiner, coupler, and balun show lower transmission loss than on-chip passives; antenna has the efficiency of over 60%. These devices on InFO enable low noise and power MMW system for mobile communication and IoT applications.

Power saving and noise reduction of 28nm CMOS RF system integration using integrated fan-out wafer level packaging (InFO-WLP) technology

An integration of 28 nm CMOS RF system with 3D solenoidal inductors (3DSI) in integrated fan-out (InFO) wafer level package technology is studied. The 3DSI provides the performance of Q-factor of 51 and isolation of -53 dB. With the 3DSI, the RF system in the InFO technology results in power saving by 58% and noise reduction by 80% in LNA and VCO, respectively, compared with those in RF SoC system. The InFO technology provides a novel solution for RF system integration.

High Performance Chip-Partitioned Millimeter Wave Passive Devices on Smooth and Fine Pitch InFO RDL

High performance millimeter wave passive devices are realized on smooth, fine pitch InFO redistribution layer (RDL). These passive devices are balun, power combiner, coupler, and microstrip line and the electrical performances are measured from 0.1GHz to 67 GHz through VNA. The measurement results show that the transmission loss of on-InFO balun (4.3 dB), the power divider (4.3 dB), and the coupler (4.9 dB) outperforms on-chip one by 2.1 dB, 1 dB, and 0.2 dB, respectively. While the transmission loss of microstrip line (0.34 dB/mm) is better than on-chip one by 0.17 dB/mm at 60 GHz. Furthermore, the parasitic of InFO chip-package interconnection has been investigated and compared to other technologies with and without solder bumps. The parasitic resistance, inductance, and capacitance for InFO interconnection are 75 %, 76 %, and 14 % lower than those for chip-last, face-down technology. Parasitic resistance for InFO RDL is 10 % lower than that for chip-first face-down technology with uneven RDL.

Taper pad design to improve electrical performance of BGAs on wafer level package (WLP)

A taper pad design is proposed to improve signal integrity in the transition from traces on chip site to PCB. Transmission loss of the transition incorporating traces, taper pads, solder balls, and microstrip line is simulated through electromagnetic simulation tool. Compared with the conventional pad design, the proposed pad design has 2 dB of improvement and only 0.9 dB insertion loss at 40 GHz. In addition, its DC/AC parasitic resistance and AC parasitic inductance are extracted and proved to have 85/65 % and 19 % of reduction, respectively, against the conventional pad design. Finally, the design guide of the proposed pad design is presented to enhance the signal integrity of WLP.