Julio Faura

A novel mixed signal programmable device with on-chip microprocessor

In this paper we present a novel field programmable mixed-signal integrated device consisting of a Field Programmable Gate Array (FPGA), a set of programmable and interconnectable analog cells, and a microprocessor core. This processor can run general purpose user programs, handle the dynamic reconfiguration of the programmable blocks and probe in real time internal digital and analog signals. The device is especially suitable for development and fast prototyping of mixed signal integrated applications.

Multicontext dynamic reconfiguration and real time probing on a novel mixed signal programmable device with on-chip microprocessor

In this paper we present a novel RAM-based field programmable mixed-signal integrated device consisting of a large granularity Field Programmable Gate Array (FPGA), a set of programmable and interconnectable analog cells, and a microprocessor core. Two configuration contexts are available, at least one of them mapped on the microprocessor memory space. The microprocessor can be used for partial (or complete) fast dynamic reconfiguration, to run general purpose user programs, and to probe in real time internal points of the analog and digital programmable hardware. The device can be partially or totally reconfigured whale it is working by loading the new configuration (including initial states for FFs) in the non-active context without stopping operation, then trasferring it to the active one in just one microprocessor write cycle.

Feasible Evolutionary and Self-Repairing Hardware by Means of the Dynamic Reconfiguration Capabilities of the FIPSOC Devices

In this paper we shall address the paradigms of evolutionary and self-repairing hardware using a new family of programmable devices, called FIPSOC (Field Programmable System On a Chip). The most salient feature of these devices is the integration on a single chip of a programmable digital section, a programmable analog section and a general-purpose microcontroller. Furthermore, the programmable digital section has been designed including a flexible and fast dynamic reconfiguration scheme. These properties provide an efficient framework for tackling the specific features posed by the emerging field of evolutionary computation. We shall demonstrate this fact by means of two different case studies: a self-repairing strategy for digital systems, suitable for applications in environments exposed to radiation, and an efficient implementation scheme for evolving parallel cellular machines.

Decoder-driven switching matrices in multicontext FPGAs: area reduction and their effect on routability

Modern FPGAs use SRAM-cells to store the programming bits that drive the switching matrices. The area of these SRAM cells can be as large as 40% of the total area. This figure dramatically increases in the case of multicontext FPGAs, where the programming configuration has to be repeated as many times as contexts. This problem is alleviated if the switches that connect an input line to several output lines in each switching block are driven by a decoder. In this case, the number of SRAM cells decreases in O(log), at the cost of routability. This paper shows with experimental results obtained from 175 benchmark circuits that, for usual FPGA parameters, routability losses are small, making the decoder-driven switch (DDS) approach an excellent method for reducing FPGA area by as much as 20%, while preserving routability.

A new field programmable system-on-a-chip for mixed signal integration

A new RAM-based, mixed-signal, multicontext dynamically reconfigurable Field Programmable Device with on-chip microprocessor is described. A completely integrated mixed-signal CAD and microprocessor programming environment is used to design and simulate electronic systems composed by microprocessor code and digital and analog hardware. The very flexible communication between the microprocessor, the configurable digital cells and the programmable analog blocks makes possible powerful integration, real-time emulation (internal signals and configuration are available to the microprocessor) and advanced run-time reconfiguration.

Approaching evolvable hardware to reality: The role of dynamic reconfiguration and virtual meso-structures

In this paper we shall address the possibility of incorporating a new degree of freedom in the design of electronic systems. It consists of providing the ability to evolve its internal meso-structure while in operation. This new design strategy is allowed by the features included in a new family of FPGA devices, which is called FIPSOC (field programmable system on a chip). Besides a programmable digital section composed of an array of LUT-like configurable cells, the device includes a configurable analog part and a general purpose microcontroller. Furthermore, the configuration scheme used for the programmable digital section allows for an efficient and fast realisation of dynamic reconfiguration principles. As we shall show in this paper, these properties offer two new on-line hardware evolution strategies, giving rise to what we have called virtual meso-structures.

Rapid prototyping of electronic systems using FIPSOC

FIPSOC (field programmable system on chip) is a novel device shown to be suitable for rapid prototyping of electronic systems. After a description of its architecture and associated development tools, its distinguishing features are highlighted. In particular, integration of a microprocessor, programmable logic and configurable analog channels in the same chip provides a monolithic platform with capability to prototype complete systems. The integrated development software and chip capabilities offer low-cost emulation on the target device, hardware and software emulation, and integrated real-time probing. An application example of a DC motor controller illustrates the benefits in cost and development time that FIPSOC can provide.

Realization of self-repairing and evolvable hardware structures by means of implicit self-configuration

In this paper we shall address the physical implementation of self-repairing and evolvable hardware strategies. These alternatives will be enabled by the specific dynamic reconfiguration capabilities included in a new family of FPGA devices, called FIPSOC (Field programmable System On a Chip). The main features of these devices are given by the integration on a single chip of a dynamically reconfigurable FPGA, a programmable analog section and a microcontroller. As our experimental results will show, the efficient use of the available resources makes these devices an excellent platform for testing, developing and realizing physically new concepts in electronic design.

The role of dynamic reconfiguration for implementing artificial neural networks models in programmable hardware

In this paper we address the problems posed when Artificial Neural Networks models are implemented in programmable digital hardware. Within this context, we shall especially emphasise the realisation of the arithmetic operators required by these models, since it constitutes the main constraint (due to the required amount of resources) found when they are to be translated into physical hardware. The dynamic reconfiguration properties (i.e., the possibility to change the functionality of the system in real time) of a new family of programmable devices called FIPSOC (Field Programmable System On a Chip) offer an efficient alternative (both in terms of area and speed) for implementing hardware accelerators. After presenting the data flow associated with a serial arithmetic unit, we shall show how its dynamic implementation in the FIPSOC device is able to outperform systems realised in conventional programmable devices.

A Bipartitioning Algorithm for Dynamic Reconfigurable Programmable Logic

Most partitioning algorithms have been developed for conventional programmable logic (especially FPGAs), being their main goal the minimisation of the signals constituting the interface (cutsize) between partitions, while balancing partition sizes. New families of dynamic reconfigurable programmable logic (DRPL) offer new possibilities to improve functional density of circuits, but traditional partitioning techniques are not able to exploit the novel features offered by these devices. A new family of partitioning techniques for DRPL should be developed, being its main goal the maximisation of the functional density on balanced partition sizes. This paper presents a new partitioning algorithm based on a temporal separation of the system functionality. As our experimental results will show, the algorithm is able to benefit from the dynamic reconfiguration properties of FPGA devices.