Christophe Maleville

Smart‐Cut® : The Basic Fabrication Process for Unibond® Soi Wafers

The advantage of SOI wafers for device manufacture has been widely studied. To be a real challenger to bulk silicon, SOI producers have to offer SOI wafers in large volume and at low cost. The new Smart‐Cut ® SOI process used for the manufacture of the Unibond® SOI wafers answers most of the SOI wafer manufacturability issues. The use of Hydrogen implantation and wafer bonding technology is the best combination to get good uniformity and high quality for both the SOI and buried oxide layer. In this paper, the Smart‐Cut ® process is described in detail and material characteristics of Unibond ® wafers such as crystalline quality, surface roughness, thin film thickness homogeneity, and electric behavior.

Extending planar device roadmap beyond node 20nm through ultra thin body technology

There is consensus in the IC industry that fully depleted devices will be the solution to the increasing challenges of device scaling towards nodes 20nm and 15nm. Fully depleted (FD) devices with undoped channels eliminate the threshold voltage VT variability due to random dopant fluctuation (RDF) reducing the overall VT variability by over 60%. For a given power supply FD devices have superior short channel behavior, exhibit significant lower leakage Ioff compared to bulk devices. These FD advantages enable an efficient power-perfomance-area (ppa) optimization at lowest VDD (e.g. ∼0.6V) which is not possible with a bulk device architecture without a significant performance and area penalty. FD devices can be planar or FinFETs. In both cases SOI substrates enable an industrial architecture of ultra thin body (UTB) devices. Planar UTB devices offer the benefits of FD behavior in conjunction with an evolutionary IC design approach but require a highly uniform SOI UTB layer. UTSOI is an industrially mature SOI substrate technology that offers a highly uniform SOI thickness layer with ±0.5nm (7 sigma) thickness uniformity. Smart Cut technology is here offering its unique advantages in integrating a thin BOX layer thru wafer bonding, while accessing atom level uniformities thru hydrogen implantation. Furthermore, SOI thickness and buried oxide (BOX) thickness are decoupled parameters and can be tuned to meet the requirements of any IC sub-32nm CMOS technology. UTSOI substrates can be produced in large volumes in existing multiple sources, then, FDSOI devices are able to offer the option of merging G and LP technology in a cost effective platform for a wide range of applications.

Smart-Cut® Technology: an Industrial Application of Ion Implantation Induced Cavities

The Smart-Cut® process is based on proton implantation and wafer bonding. Proton implantation enables delamination of a thin layer from a thick substrate to be achieved whereas the wafer bonding technique enables different multilayer structures to be achieved by transferring the delaminated layer onto a second substrate. One of the best known applications of Smart Cut® is the Silicon On Insulator structure. The physical mechanisms involved in the delamination process are discussed based on the study of Proton-induced microcavity formation during implantation and growth during annealing. The experimental results on the time and temperature required to achieve delamination lead to different activation energies depending on the implantation conditions and resistivity of the substrate. All the experiments indicate that growth of microcavities is mainly controlled by hydrogen diffusion. The growth of these microcavities and the pressure inside them induce delamination when the catastrophic radius of the microcavities is reached.

SOI substrate readiness for 22/20 nm and for fully depleted planar device architectures

Fully depleted (FD) MOSFET architecture for sub-32 nm technology node requires a new SOI substrate fabrication to meet all the stringent specifications imposed by a FD device. Ultra Thin SOI (UTSOI) targets planar device architectures, stressing specifications for thickness uniformity. Also Ultra Thin Burried Oxyde (UTBOx) offers additional benefits such as the application of back bias, for example enhancing device stability or threshold voltage tuning. In this paper, we discuss the Smart CutTM technology capability for both UTSOI and UTBOx substrate design with the quality and specifications that meet the future FD technology requirements.

Strained silicon on insulator substrates for fully depleted application

Smart Cut™ technology is used to manufacture Strained-SOI (sSOI) substrates. These substrates are proposed to boost performance for both planar and FinFET Fully Depleted SOI devices. To comply with tight transistor variability requirements, strong emphasis has been put on layer thickness control and low stress variation. A 1.2 Å RMS roughness and less than 10% stress fluctuation are already demonstrated for sSOI wafers.

Excellent silicon thickness uniformity on Ultra-Thin SOI for controlling Vt variation of FDSOI

Thickness uniformity of the Ultra Thin SOI (UTSOI) substrates is one of the key criteria to control Vt variation of the planar FDSOI devices. We present an evolutionary approach to SmartCutTM technology which already allows achieving a maximum total SOI layer thickness variation of less than ± 10 Å on preproduction volume. Total thickness variation of ± 5 Å is targeted.

Multiple SOI layers by multiple Smart-Cut/sup (R)/ transfers

Silicon on insulator (SOI) technologies are now entering mainstream applications, with recent announcements regarding for instance microprocessor applications. One condition for this to happen has been proof that SOI material manufacturing processes exist that are compatible with such industrial developments (availability, cost, quality, etc.). Among those processes, the Smart-Cut/sup (R)/ process is based on layer transfer from one substrate to another (Bruel, 1996). Stacking monocrystalline silicon on another silicon substrate with a silica layer in between is then possible and indeed is being used on a industrial scale to manufacture SOI wafers. Beyond simple SOI wafers that can also be high value added substrates for other applications such as photonics, sensors and other micromachining purposes, we demonstrate in this paper how the Smart-Cut/sup (R)/ process can be seen as a basic step and how this process can be used to realize multiple SOI wafers, allowing different crystalline and/or amorphous layers to be stacked.

Direct wafer bonding for nanostructure preparations

Direct Wafer Bonding has been widely developed and is very attractive for a lot of applications. Using original techniques based on direct bonding enable to carry out specific engineered substrates. Various illustrations are given among which twisted Si-Si bonded substrates, where buried dislocation networks play a key role in the subsequent elaboration of nanostructures.

Defect detection on SOI wafers using laser scattering tools

Laser scattering tools are used in production monitoring of wafer defectivity. We present SOI wafer specific behavior related to the intrinsic limitations of laser scattering defect detection. An empiric model of accessible thresholds regarding layer thickness is proposed. When removing roughness induced haze on an SOI structure, the haze level of SOI wafers is clearly linked with structure reflectivity. Since the haze varies in the reverse order of the reflectivity, the defect measurement threshold needs to be adapted to avoid reflectivity induced false counts in wafer characterization. Wafer uniformity must also be considered when choosing the measurement threshold, especially in the case of very thin silicon layers, typically targeted for fully depleted applications. For these advanced applications the laser used in detection tools will have to move to UV light in order to reach detection limits under 0.16 /spl mu/m as required by ITRS roadmaps.

Cleaning and polishing as key steps for Smart-cut(R) SOI process

Silicon on insulator technologies appear to be suitable for low power and low voltage electronics. SIMOX wafers have been considered as the best candidates to realize ULSI devices. An alternative route has been proposed by M. Bruel (1995-96) referred to as the Smart-cut process. This new process is versatile enough to fabricate SOI structures (Unibond wafers) with tuned silicon and oxide layer thicknesses. Good thickness homogeneity, low defect density, high surface quality and good electrical properties are now available in these SOI wafers. The authors show that most of these parameters depend, to some degree, on the cleaning step before wafer bonding or on the final chemical mechanical polishing process. As an example, surface roughness and defect densities are investigated by comparison with SIMOX wafer results.