Erick Guerrero

A Low-Power CMOS Receiver for 1.25 Gb/s Over 1- mm SI-POF Links

This paper presents an optical receiver for short-reach applications through low-cost plastic optical fiber. The limited bandwidth caused by the fiber and the external photodiode is compensated by a new adaptive equalizer based on the spectrum balancing technique. A clock and data recovery circuit is included that minimizes jitter and metastability using a new multilevel bang-bang architecture. The prototype, implemented in a standard 0.18-μm CMOS process, achieves 1.25 Gb/s with a power of 107 mW at only 1 V.

A 1-V 1.25-Gbps CMOS analog front-end for short reach optical links

This paper presents a new adaptive equalizer for short reach applications through low-cost plastic optical fiber. The adaptive equalizer uses the spectrum balancing technique to compensate the limited bandwidth caused by the fiber and the external photodiode. The prototype has been implemented in a standard 0.18-μm CMOS process fed at 1 V. It consumes 38.6 mW at 1.25 Gb/s.

A 2.5-Gb/s multi-rate continuous-time adaptive equalizer for short reach optical links

This paper presents a new multi-rate continuous-time adaptive equalizer for short-haul gigabit optical communications. It is designed to compensate the attenuation of a 50-m 1-mm core step-index plastic optical fiber (SI-POF) for input data ranges from 400 Mb/s up to 2.5 Gb/s. It includes three adaptation loops to compensate the possible variations in level and spectrum of the input signal. The prototype has been implemented in a cost-effective 0.18-μm CMOS process. The system is fed with only 1 V and has a total power consumption of 60 mW.

A fully-differential adaptive equalizer using the spectrum-balancing technique

A low-voltage high-speed CMOS fully-differential adaptive equalizer based on the spectrum-balancing technique is presented in this paper. It was designed to compensate the strong attenuation of the transmitted signal due to fiber losses. The proposed equalizer, formed by a line equalizer and an adaptation loop, targets 2.5 Gb/s transmission for a simple NRZ modulation through a 50-m SI-POF. It was designed in a 0.18-μm standard CMOS process, fed with 1V and has a power consumption below 17.3 mW.

Continuous-Time Linear Equalizer for Multigigabit Transmission Through SI-POF in Factory Area Networks

This letter presents a new complimentary metal-oxide-semiconductor analog continuous-time equalizer aimed to compensate the limited frequency response of step-index polymer optical fiber (SI-POF), a transmission medium very attractive for industrial applications as factory automation and process control networks because of its cost and immunity to electromagnetic interference. The structure overcomes the limitations of the most widely used continuous-time equalizer, the degenerated differential pair, for 1-V supply voltage. The linear equalizer has been proved for multigigabit short-range applications targeting up to 2 Gb/s through a 50-m SI-POF. The prototype consumes 2.7 mW.

Precoder and decoder for duobinary modulation over equalized 50-m SI-POF

This work presents a novel CMOS transceiver that enables 50-m 1-mm step-index plastic optical fiber (SI-POF) to increase transmitted data rate up to 3.125 Gbps using amplitude duobinary modulation, in addition to continuous-time equalization. For that purpose, a duobinary precoder and a duobinary decoder have been designed in a cost-effective 0.18-μm CMOS technology fed with 1.8 V, consuming 27.9 mW in total. Additionally, a new model based on low-pass Bessel filter has been proposed to simulate the effect of the equalized channel, achieving excellent agreement with experimental data. Post-layout results validate the advantages of the proposed transceiver.

Single-Chip Receiver for 1.25 Gb/s Over 50-m SI-POF

This letter presents a single chip receiver for short-reach high-speed applications through low-cost plastic optical fiber. It compensates the limited bandwidth caused by the fiber and the external photodiode. The prototype contains a transimpedance amplifier, a continuous-time adaptive equalizer, a limiting amplifier, and a clock and data recovery circuit. Experimentally, we have obtained 1.25 Gb/s transmission for a simple nonreturn to zero modulation in an optical link composed of 50 m of step-index polymer optical fiber and a large area Si p-i-n photodetector. It achieves a power under 110 mW at only 1 V of supply voltage.

Continuous-time equalizer for CMOS integrated photodiodes

Fully integrated optoelectronic interfaces in CMOS technology are a very interesting option for optical smart sensors because they are a cost-effective and compact solution. However, CMOS standard n-well/p-bulk differential photodiodes (DPDs) are the bottleneck in this field due to their inherent limited bandwidth which falls below 10MHz in 65nm CMOS. This work presents a new equalization approach to enhance the bandwidth of CMOS integrated DPDs used in optical sensors. It is designed based on a split-path topology in which the gain and the boost are completely decoupled and can be externally adjusted by means of independent control voltages. This feature, particularly helpful for calibration, is not present in conventional equalizers based on the degenerated differential pair. The proposed equalization technique has been simulated in a 65nm process, where it has been able to increase the bandwidth of the DPD from their inherent 10MHz up to 3GHz with a single supply voltage of only 1.2V.

An Adaptive Bitrate Clock and Data Recovery Circuit for Communication Signal Analyzers

Many measurement instruments require an external timing reference to perform an accurate measurement. In equivalent-time oscilloscopes, for example, a trigger signal properly aligned to the data is essential, since they base their operation on a very accurate delay of the trigger, which is obtained by a clock and data recovery (CDR) circuit. In this paper, an adaptive bitrate CDR circuit for instrumentation applications is presented. It is designed in a standard 0.18-μm CMOS technology with a single supply voltage of 1.8 V and operates from 312.5 Mb/s to 2.5 Gb/s with a maximum power consumption of 140 mW and occupies an area of 1.5 mm × 0.6 mm.

1-V continuous-time linear equalizer for up to 2 Gb/s over 50-m SI-POF

In this paper, we present a new CMOS analog continuous-time linear equalizer. The proposed structure overcomes some of the limitations due to the low supply voltage of the most widely used continuous-time equalizer, the degenerated differential pair. The prototype has been tested for multi-gigabit short-range applications targeting up to 2 Gb/s through a 50-m SI-POF. The proposed linear equalizer was designed in a cost-effective 90-nm CMOS process. The system is fed with a single supply voltage of 1 V and consumes 2.7 mW.