Javier Aguirre

Square-Signal-Based Algorithm for Analog Lock-In Amplifiers

Dual-phase lock-in amplifiers (LIAs) are designed to extract information (amplitude and phase) from signals buried in high noise levels. In spite of their popularity, their use has been traditionally limited to input sinusoidal waves with symmetric power supplies. This paper presents an algorithm that enables single-supply analog LIAs to properly process input square waves. Formed by linear equations, its computational implementation is much simpler than that of the traditional sinusoidal algorithm. Moreover, applied to battery-operated microcontrolled systems where square signals can be generated by the embedded microcontroller, it presents intrinsic advantages such as simplicity, versatility, and reduction in power and size. Experimental results validate the proposed algorithm, confirming its enormous possibilities in sensing applications.

Erodibility and Hydrology of Arid Burned Soils: Soil Type and Revegetation Effects

A set of experiments with a rainfall simulator was performed in the field to evaluate the efficiency of parallel contour seeding as a post-fire restoration strategy in the arid central Ebro Valley (NE Spain). Rainfall simulations were conducted in spring, after seeded plant development, on calcareous and gypsiferous soils, with the same experimental design (two-soil treatments—seeded and nonseeded—per two soil types and per nine replicates). The parallel contour seeding treatment increases soil cover and soil surface roughness, which significantly ameliorates the hydrological and erosional response of both calcareous and gypsiferous burned soils. Seeding decreased soil loss, both in calcareous (23-fold) and gypsiferous soils (4-fold). In addition, it decreased the sediment concentration of runoff for calcareous (6-fold) and gypsiferous soils (2-fold) and the runoff coefficient for calcareous (3.5-fold) and gypsiferous soils (1.5-fold). On the other hand, seeding increased the steady state infiltration rate (3-fold), as well as surface soil moisture (1.2-fold) and wetting front depth (2-fold), with a similar order of magnitude for both soils. Time to runoff and runoff quality (electrical conductivity [EC] and pH) were not affected by seeding. Gypsiferous soils had a higher soil loss, runoff coefficient, and EC flow and a lower time to runoff, steady state infiltration rate, and wetting front depth than calcareous soils. Some of these differences were directly related to differences in soil gypsum and carbonate content (i.e., EC and pH of water runoff) and others are related to the proportion of surface soil protection, an indirect effect of soil characteristics. The results suggest that parallel contour seeding is an effective restoration measure with a short-term response that allows conservation of water and soil on recently burned arid lands, especially in situations of high erosion risk as occurs with soils with low plant cover.

A 1.7-GHz wide-band CMOS LC-VCO with 7-Bit coarse control

This paper presents an LC-tank-based voltage-controlled oscillator, fabricated in a standard 0.18 μm CMOS technology, with a 44 % tuning range around a center frequency of 1.7 GHz. To minimize the impact of the proposed oscillator on phase noise in phase-locked-loops, it has a coarse control of 27-1 levels, driven by a 7-bit digital word, achieving a tuning sensitivity below 35 MHz/V along the whole tuning range. The oscillator has -123.4 dBc/Hz phase noise at 1 MHz offset and draws 10 mA from a 1.8 V supply, yielding a total power/tuning/frequency-normalized figure of merit equal to -5.5 dB.

A 2.5-Gb/s multi-rate continuous-time adaptive equalizer for short reach optical links

This paper presents a new multi-rate continuous-time adaptive equalizer for short-haul gigabit optical communications. It is designed to compensate the attenuation of a 50-m 1-mm core step-index plastic optical fiber (SI-POF) for input data ranges from 400 Mb/s up to 2.5 Gb/s. It includes three adaptation loops to compensate the possible variations in level and spectrum of the input signal. The prototype has been implemented in a cost-effective 0.18-μm CMOS process. The system is fed with only 1 V and has a total power consumption of 60 mW.

A 3V single supply LIA for portable sensing systems

This work presents a 3 V single supply analog lock-in amplifier designed for processing output sensor signals in highly noisy environments. The proposed amplifier uses square input signals instead of the usual sinusoidal signals, consequently allowing a straight interface with microcontroller-based sensing systems, and can be utilized for both resistive and capacitive sensors since it is based on a dual channel rectifier to remove phase dependence of the sensor signal. Experimental results for signals buried in white noise, flicker noise, interference contamination and common-mode voltage contamination confirm the capability of the proposed solution to effectively recover information from signal to noise ratios down to −24 dB with errors below 6% with an average power consumption of only 5 mW in full operation.

Precoder and decoder for duobinary modulation over equalized 50-m SI-POF

This work presents a novel CMOS transceiver that enables 50-m 1-mm step-index plastic optical fiber (SI-POF) to increase transmitted data rate up to 3.125 Gbps using amplitude duobinary modulation, in addition to continuous-time equalization. For that purpose, a duobinary precoder and a duobinary decoder have been designed in a cost-effective 0.18-μm CMOS technology fed with 1.8 V, consuming 27.9 mW in total. Additionally, a new model based on low-pass Bessel filter has been proposed to simulate the effect of the equalized channel, achieving excellent agreement with experimental data. Post-layout results validate the advantages of the proposed transceiver.

Single-Chip Receiver for 1.25 Gb/s Over 50-m SI-POF

This letter presents a single chip receiver for short-reach high-speed applications through low-cost plastic optical fiber. It compensates the limited bandwidth caused by the fiber and the external photodiode. The prototype contains a transimpedance amplifier, a continuous-time adaptive equalizer, a limiting amplifier, and a clock and data recovery circuit. Experimentally, we have obtained 1.25 Gb/s transmission for a simple nonreturn to zero modulation in an optical link composed of 50 m of step-index polymer optical fiber and a large area Si p-i-n photodetector. It achieves a power under 110 mW at only 1 V of supply voltage.

Continuous-time equalizer for CMOS integrated photodiodes

Fully integrated optoelectronic interfaces in CMOS technology are a very interesting option for optical smart sensors because they are a cost-effective and compact solution. However, CMOS standard n-well/p-bulk differential photodiodes (DPDs) are the bottleneck in this field due to their inherent limited bandwidth which falls below 10MHz in 65nm CMOS. This work presents a new equalization approach to enhance the bandwidth of CMOS integrated DPDs used in optical sensors. It is designed based on a split-path topology in which the gain and the boost are completely decoupled and can be externally adjusted by means of independent control voltages. This feature, particularly helpful for calibration, is not present in conventional equalizers based on the degenerated differential pair. The proposed equalization technique has been simulated in a 65nm process, where it has been able to increase the bandwidth of the DPD from their inherent 10MHz up to 3GHz with a single supply voltage of only 1.2V.

An Adaptive Bitrate Clock and Data Recovery Circuit for Communication Signal Analyzers

Many measurement instruments require an external timing reference to perform an accurate measurement. In equivalent-time oscilloscopes, for example, a trigger signal properly aligned to the data is essential, since they base their operation on a very accurate delay of the trigger, which is obtained by a clock and data recovery (CDR) circuit. In this paper, an adaptive bitrate CDR circuit for instrumentation applications is presented. It is designed in a standard 0.18-μm CMOS technology with a single supply voltage of 1.8 V and operates from 312.5 Mb/s to 2.5 Gb/s with a maximum power consumption of 140 mW and occupies an area of 1.5 mm × 0.6 mm.

An analog lock-in amplifier for embedded sensor electronic interfaces

This paper presents a single supply analog lock-in amplifier for processing sensor noisy signals in low-voltage low-power embedded applications. The proposed system is based on a dual channel architecture to eliminate the phase dependence and enable its use for both resistive and capacitive sensors. In addition, looking for a compact solution, instead of a sinusoidal input a square wave input which can be directly obtained from one of the outputs of the embedded microcontroller is considered. Experimental results for tests conducted with white noise, flicker noise, interference contamination and common-mode voltage contamination confirm the capability of the proposed amplifier to effectively recover information from signal to noise ratios below −24dB with errors below 6%.