Wim Verhaegen

Fast, layout-inclusive analog circuit synthesis using pre-compiled parasitic-aware symbolic performance models

We present a new methodology for fast analog circuit synthesis, based on the use of parameterized layout generators and symbolic performance models (SPMs) in the synthesis loop. Fast layout generation is achieved by using efficient parameterized procedural layout generators. Fast performance estimation is achieved by using pre-compiled SPMs, stored as efficient DDD-like structures called element coefficient diagrams. Techniques have been developed to include layout geometry effects in the SPMs. The accuracy and efficiency of the parasitic inclusion technique as well as the proposed methodology have been demonstrated by comparisons to traditional synthesis methods. The proposed methodology is used for the synthesis of opamps and filters and is demonstrated to achieve effective performance closure.

Evaluation of error-control strategies for the linear symbolic analysis of analog integrated circuits

The generation of approximate linear symbolic expressions for analog integrated circuits requires the use of an appropriate error-control strategy. The error-control strategy determines both correctness and compactness of the approximate expression. This paper presents an evaluation of different error-control strategies that fit within the flat symbolic analysis, using simplification during generation techniques for large analog integrated circuits. The theoretical exposition is illustrated with experimental results that allow a comparison of the proposed methods.

Automated test pattern generation for analog integrated circuits

An algorithm for the generation of tests for analog integrated circuits is proposed. It starts from a generated fault list and ranges specified by the user and determines optimal test signals that maximize the detectability of all faults. As statistical fluctuations have to be considered when evaluating analog circuits, it is based on a statistical test criterion. Two examples demonstrate the practical use and versatility of this approach.

Use of symbolic performance models in layout-inclusive RF low noise amplifier synthesis

We present a layout-in-loop synthesis method for radio-frequency LNAs, which uses symbolic performance models (SPMs), parameterized layout generator and high-frequency extraction techniques in the synthesis loop. The primary focus of this work is on performance estimation using efficient SPMs and development of techniques to include layout parasitics symbolically into the SPMs before the start of synthesis. SPMs for noise figure and distortion parameters are obtained using repetitive and weakly nonlinear symbolic analysis and are stored as pre-compiled element coefficient diagrams (ECDs). Speedy layout generation is achieved by using parameterized procedural layout generators and full parasitic extraction is done by using multiple extractors. Quasi-static extraction is used to obtain the critical parasitic effects of interconnects and on-chip inductors. The proposed methodology is used for the synthesis of low noise amplifiers (LNAs).

Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams

This paper presents a new method to perform efficient-first-order symbolic sensitivity analysis of analog circuits by direct differentiation of symbolic expressions stored as element-coefficient diagrams (ECDs). An ECD is a compact graphical representation of a symbolic transfer function. It is the cancellation-free and per-coefficient term generation version of determinant decision diagrams (DDDs). The symbolic sensitivity equations obtained from ECDs are stored as a sensitivity-ECDs (SECDs) and can be evaluated extremely fast as it inherits the properties of ECDs. The proposed methodology has been applied to the calculation of sensitivities of four benchmark circuits and it has been demonstrated to be as accurate and more efficient than numerical sensitivity analysis done by SPECTRE.

Efficient DDD-based symbolic analysis of large linear analog circuits

A new technique for generating approximate symbolic expressions for network functions in linear(ized) analog circuits is presented. It is based on the compact determinant decision diagram (DDD) representation of the circuit. An implementation of a term generation algorithm is given and its performance is compared to a matroid-based algorithm. Experimental results indicate that our approach is the fastest reported algorithm so far for this application.

Statistical behavioral modeling for A/D-converters

An automated method to derive the statistical parameters of the building blocks of A/D-converters is presented. This method is applied to an 8-bit full flash A/D-converter. The statistical model is used to simulate INL and DNL and explore statistical effects that cannot be captured in closed expressions. A speedup in simulation times of over 100 is reported compared to device-level simulations.

Symbolic Determinant Decision Diagrams and Their Use for Symbolic Modeling of Linear Analog Integrated Circuits

An efficient technique for the symbolic modeling of the frequency behavior of a linearized analog circuit is presented. It uses a compact graph representation based on the Laplace expansion of the system determinant, called determinant decision diagram or DDD. The construction of a circuits DDD is explained and an analysis of the time and space complexity is given. These DDDs can be used in behavioral modeling by representing the exact numerical transfer function in a compact way. DDDs also enable the generation of symbolic transfer functions, resulting in a symbolic analysis technique with lower computational complexity than techniques not based on DDDs.

Fully-coupled 3D electro-thermal field simulator for chip-level analysis of power devices

The paper presents a novel approach to modelling static and dynamic electro-thermal effects in large integrated and discrete semiconductor power devices. Electrical and thermal equations are solved simultaneously and selfconsistently from a single set of equations. A high spatial resolution allows accurate modelling of metal layers as required for advanced integrated BCD technologies. The simulator uses a well-adapted mesh for the substrate, which is important for the simulation of the temperature. Thus, both the voltage drop in the on-chip metallization as well as the device temperatures can accurately be determined without sacrificing accuracy or limiting the applicability of the simulator to special cases. Electrical and thermal conductivities of both metal and substrate are temperature dependent. Measurement and simulation results for test chips and real DMOS driver stages with small integrated temperature sensors are presented. An excellent match is observed even for very high temperatures exceeding 300°C. The tool integrates easily in an industrial design environment with direct import of GDS layout and ITF technology data.

Efficient symbolic analysis of analog integrated circuits using determinant decision diagrams

A new approach towards symbolic circuit analysis is presented. It is inspired by the concept of zero suppressed binary decision diagrams (ZBDDs) which is used in digital synthesis for representing functions in combinatorial logic in a minimal way. It is shown that this approach can be used for representing transfer functions of analog small-signal circuits, and moreover that efficient algorithms can be implemented for the manipulation of ZBDDs. As an example, the generation of the dominant terms of the coefficients of a transfer function has been implemented. It is shown that this approach is more efficient than other reported methods.