Erwin B. Cohen

Hotspot-Limited Microprocessors: Direct Temperature and Power Distribution Measurements

An experimental technique is presented, which allows for spatially-resolved imaging of microprocessor power (SIMP). In a first step this method utilizes infrared (IR) thermal imaging, while the processor is effectively cooled using an IR-transparent heat sink. In the second step the underlying power distribution is derived by determining the temperature fields for each individual power source on the chip. The measured chip temperature distribution is represented as a superposition of these temperature fields. The SIMP data reveals significant temporal and spatial variations of the microprocessor power/temperature distribution, which can be attributed to the circuit layout as well as to the varying utilization levels across the processor while running full workloads. In this paper we have applied the SIMP method to the dual core PowerPCtrade970MP microprocessor to measure detailed temperature and power distributions under full operating conditions. In the first part of the paper the impact of power and temperature limitations of high performance CMOS chips is discussed in detail, where we distinguish between hotspot-limited (or temperature-limited) and power-limited chips. The discussion shows the importance of temperature and power distributions for chip floor planning, layout, design and architecture. Second, we present the experimental details of the SIMP method, which is applied to the dual core PowerPC970MP to directly measure the temperature and power fields as a function of workload and frequency. A pronounced movement of the hotspot location is observed. Finally, the hotspot of a competitive microprocessor is compared by measuring temperature efficiencies (temperature increase/performance) for the same workloads and cooling conditions

PowerTune: advanced frequency and power scaling on 64b PowerPC microprocessor

PowerTune is a power-management technique for a multi-gigahertz superscalar 64b PowerPC/sup /spl reg// processor in a 90nm technology. This paper discusses the challenges and implementation of a dynamically controlled clock frequency with noise suppression as well as a synchronization circuit for a multi-processor system.

PowerPC 970 in 130 nm and 90 nm technologies

A 64 b PowerPC microprocessor is introduced in 130 nm and redesigned in 90 nm SOI technology. PowerPC 970 implements a SIMD instruction set with 512 kB L2 cache. It runs at 2.0 GHz with a 1.0 GHz bus in 130 nm. The 90 nm design features PowerTune for rapid frequency and power scaling and electronic fuses.

Power Distribution Measurements of the Dual Core PowerPC/sup TM/ 970MP Microprocessor

Spatially-resolved imaging of microprocessor power (SIMP) is shown to be a critical tool for measuring temperature and power distributions of a microprocessor under full operating conditions. In this paper, the SIMP technique is applied to the dual-core PowerPCtrade 970MP microprocessor

A 64-bit microprocessor in 130-nm and 90-nm technologies with power management features

The first two members in a family of 64-bit superscalar microprocessors are presented. The 130-nm processor, which was introduced first, offers 5-way instruction dispatch, support for 4-way integer and floating-point single-instruction multiple-data (SIMD) operations, a 512-kB second level (L2) cache, and a high-speed external bus. The 90-nm processor is a technology remap of the 130-nm design. It retains the features of the 130-nm processor and adds others, including a new power management facility. The architecture, device characteristics, power management, and thermal details of these two processors are described. In addition, the dataflow layout, aspects of the circuit design, clocking, and timing are discussed.

A 64B CPU Pair: Dual- and Single-Processor Chips

Two Powertrade-architecture 64b microprocessor chips are fabricated in 90nm dual strained-silicon SOI technology. The dual-processor chip has split clock domains and power planes, 1 MB L2 cache per core and a shared processor interconnect bus. The single-processor chip shares the duals basic core and cache design

Temperature-limited microprocessors: Measurements and design implications

The details of the power distribution of state of the art CMOS chips (e.g., local regions of high power (or hotspots), which disproportionally drive up junction temperatures) can have a severe impact on reliability, manufacturing yield and chip performances. In this paper we discuss the results of a recently developed technique (spatially-resolved imaging of microprocessor power (SIMP)), which can measure power and temperature distributions of high power chips (e.g., microprocessors) under full operating conditions. Specifically, we present detailed microprocessor power distributions for different workloads with and without power/thermal management. The data yields a more comprehensive understanding of the relationships between hotspots and the respective designs, layouts, floorplans, micro-architectures and thermal/power management schemes, which is discussed in detail