Miles G. Canada

A 480 MHz RISC microprocessor in a 0.12 /spl mu/m L/sub eff/ CMOS technology with copper interconnects

A 32 b 480 MHz PowerPC reduced-instruction-set-computer (RISC) microprocessor is migrated into an advanced 0.2 /spl mu/m CMOS technology with copper interconnects and multi-threshold transistors. These technology features have helped to increase the microprocessor internal clock frequency to 480 MHz at 2.0 V and 85/spl deg/C, and at the fast end of the process distribution. When operating at room temperature, the clock frequency increases to over 500 MHz. The microprocessor architecture includes two 32 KB L1 caches, one for data and one for instructions, integrated L2 cache controller working with L2 caches of 256 KB, 512 KB, or 1MB, and I/Os interfacing with the external bus using industry-standard 3.3 V. The microprocessor is implemented in 2.5 V CMOS technology and has migrated to 1.8 V CMOS technology.

A 580 MHz RISC microprocessor in SOI

A RISC microprocessor remapped in SOI technology exploits the advantages of SOI to boost processor frequency by 20% to 580MHz at 2.0V and 85/spl deg/C and fast process. The separation by implanted oxygen (SIMOX) SOI process produces partially-depleted devices. Source and drain capacitances are reduced by an order of magnitude, improving gate delay by 12%. Reduction in body-bias effects on device stacks and passgate topologies results in an additional 15%-25% improvement. Speed gains of up to 35% are achieved in some designs. The frequency-limiting paths in this processor are dominated by SRAM access and self-timed dynamic circuits whose timing had to be relaxed to guarantee functionality.

PowerTune: advanced frequency and power scaling on 64b PowerPC microprocessor

PowerTune is a power-management technique for a multi-gigahertz superscalar 64b PowerPC/sup /spl reg// processor in a 90nm technology. This paper discusses the challenges and implementation of a dynamically controlled clock frequency with noise suppression as well as a synchronization circuit for a multi-processor system.

PowerPC 970 in 130 nm and 90 nm technologies

A 64 b PowerPC microprocessor is introduced in 130 nm and redesigned in 90 nm SOI technology. PowerPC 970 implements a SIMD instruction set with 512 kB L2 cache. It runs at 2.0 GHz with a 1.0 GHz bus in 130 nm. The 90 nm design features PowerTune for rapid frequency and power scaling and electronic fuses.

A 64-bit microprocessor in 130-nm and 90-nm technologies with power management features

The first two members in a family of 64-bit superscalar microprocessors are presented. The 130-nm processor, which was introduced first, offers 5-way instruction dispatch, support for 4-way integer and floating-point single-instruction multiple-data (SIMD) operations, a 512-kB second level (L2) cache, and a high-speed external bus. The 90-nm processor is a technology remap of the 130-nm design. It retains the features of the 130-nm processor and adds others, including a new power management facility. The architecture, device characteristics, power management, and thermal details of these two processors are described. In addition, the dataflow layout, aspects of the circuit design, clocking, and timing are discussed.

A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor

Increasing demand for parallelism due to out-of-order and multi-threading computation requires fast and dense arrays with multi-port capabilities. The load-store-unit (LSU) of the POWER7™ microprocessor core has a 32kB L1 data cache composed of four 8kB blocks. In a two-cycle back-to-back operation it supports concurrently two independent read and one write operations. Organized in banks of 16 cells each, the two reads operate independently in any of these banks, including two reads within the same bank, even the same cell. A bank selected for write is blocked for any read operation. If read and write collide within the same bank, collision-control circuitry provides write-over-read priority. Each read port provides 4B from 1 of 256 locations, whereas the double-bandwidth write operation provides individual control of 8B to 128 locations.

A 64B CPU Pair: Dual- and Single-Processor Chips

Two Powertrade-architecture 64b microprocessor chips are fabricated in 90nm dual strained-silicon SOI technology. The dual-processor chip has split clock domains and power planes, 1 MB L2 cache per core and a shared processor interconnect bus. The single-processor chip shares the duals basic core and cache design