Paul David Kartschoke

A 480 MHz RISC microprocessor in a 0.12 /spl mu/m L/sub eff/ CMOS technology with copper interconnects

A 32 b 480 MHz PowerPC reduced-instruction-set-computer (RISC) microprocessor is migrated into an advanced 0.2 /spl mu/m CMOS technology with copper interconnects and multi-threshold transistors. These technology features have helped to increase the microprocessor internal clock frequency to 480 MHz at 2.0 V and 85/spl deg/C, and at the fast end of the process distribution. When operating at room temperature, the clock frequency increases to over 500 MHz. The microprocessor architecture includes two 32 KB L1 caches, one for data and one for instructions, integrated L2 cache controller working with L2 caches of 256 KB, 512 KB, or 1MB, and I/Os interfacing with the external bus using industry-standard 3.3 V. The microprocessor is implemented in 2.5 V CMOS technology and has migrated to 1.8 V CMOS technology.

A 580 MHz RISC microprocessor in SOI

A RISC microprocessor remapped in SOI technology exploits the advantages of SOI to boost processor frequency by 20% to 580MHz at 2.0V and 85/spl deg/C and fast process. The separation by implanted oxygen (SIMOX) SOI process produces partially-depleted devices. Source and drain capacitances are reduced by an order of magnitude, improving gate delay by 12%. Reduction in body-bias effects on device stacks and passgate topologies results in an additional 15%-25% improvement. Speed gains of up to 35% are achieved in some designs. The frequency-limiting paths in this processor are dominated by SRAM access and self-timed dynamic circuits whose timing had to be relaxed to guarantee functionality.

PowerPC 970 in 130 nm and 90 nm technologies

A 64 b PowerPC microprocessor is introduced in 130 nm and redesigned in 90 nm SOI technology. PowerPC 970 implements a SIMD instruction set with 512 kB L2 cache. It runs at 2.0 GHz with a 1.0 GHz bus in 130 nm. The 90 nm design features PowerTune for rapid frequency and power scaling and electronic fuses.

A 64-bit microprocessor in 130-nm and 90-nm technologies with power management features

The first two members in a family of 64-bit superscalar microprocessors are presented. The 130-nm processor, which was introduced first, offers 5-way instruction dispatch, support for 4-way integer and floating-point single-instruction multiple-data (SIMD) operations, a 512-kB second level (L2) cache, and a high-speed external bus. The 90-nm processor is a technology remap of the 130-nm design. It retains the features of the 130-nm processor and adds others, including a new power management facility. The architecture, device characteristics, power management, and thermal details of these two processors are described. In addition, the dataflow layout, aspects of the circuit design, clocking, and timing are discussed.

A 64B CPU Pair: Dual- and Single-Processor Chips

Two Powertrade-architecture 64b microprocessor chips are fabricated in 90nm dual strained-silicon SOI technology. The dual-processor chip has split clock domains and power planes, 1 MB L2 cache per core and a shared processor interconnect bus. The single-processor chip shares the duals basic core and cache design

Techniques that improved the timing convergence of the Gekko PowerPC microprocessor

Wire capacitance models used in some synthesis tools have been based on number of fanouts. These wire capacitance models can be misleading when compared to real wiring. This discrepancy can cause synthesis tools to optimize incorrectly causing severe problems with chip level timing convergence. Designs may take longer than expected and designers may work on timing paths that are not critical thus increasing the design cycle. In sub-micron designs it is crucial to improve the timing convergence between synthesis and physical design. This paper describes several practical approaches used in timing convergence of the IBM Gekko PowerPC/sup 1/ microprocessor that is used in the Nintendo Gamecube system. The impact of each approach is evaluated on the timing and size of the microprocessor.

Timing driven wiring on an advanced microprocessor

The effect of wire delay within critical timing paths is becoming an increasing problem. By comparing the large improvement of transistor performance, due to shrinking L/sub eff/ or new technology such as silicon on insulator, versus the smaller improvements of wire delay, such as copper wires and better dielectrics, it can be seen that the wiring within an advanced microprocessor will become a more dominant portion of the critical paths. In deep sub-micron designs it is crucial to analyze and improve any wire dominated paths while assuming that the transistor delay continues to improve. This paper describes wire related improvements, such as an algorithmic wiring approach, wire bending and clock skew reduction that is used in the timing convergence of an advanced PowerPC microprocessor. The impact of wiring improvements is evaluated on the timing, clocking and wireability of the microprocessor.

Techniques for improving timing convergence of advanced microprocessors

The wire capacitance models that are used in synthesis tools are typically based on the number of fanouts. These wire capacitance models can be misleading when compared to real wiring. This discrepancy can cause synthesis tools to optimize incorrectly, causing severe problems with chip-level timing convergence. Designs may take longer than expected and designers may work on timing paths that are not critical, thus increasing the design cycle time. In submicron designs, it is crucial to improve the timing convergence between the synthesis and the physical design. This paper describes several practical approaches used in the timing convergence of an advanced PowerPC microprocessor. The impact of each approach is evaluated on the timing and the size of the microprocessor.