Eun-ji Jung

17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization

The power consumption of a mobile application processor (AP) is strongly limited by the SRAM minimum operating voltage, VMIN [1], since the 6T bit cell must balance between write-ability and bit cell stability. However, the SRAM VMIN scales down gradually with advanced process nodes due to increased variability. This is evident with the quantized device-width and limited process-knobs of a FinFET technology, which has greatly affected SRAM design [2-4]. Therefore, assist-circuits are more crucial in a FinFET technology to improve VMIN, which in turn adds to the Power, Performance, and Area (PPA) gain of SRAM.

Investigation of Chemical Vapor Deposition (CVD)-Derived Cobalt Silicidation for the Improvement of Contact Resistance

The improved contact resistance was obtained by the new barrier metal scheme such as CVD-Co/Ti/TiN process in the level of about half of that from CVD-Ti/TiN process. And the mechanism of contact silicidation of CVD-Co/Ti/TiN was investigated. Because Co silicide may prohibit the Si diffusion into Ti silicide and Si recess during TiCl4-based CVD-Ti process, and the inertness of Co silicide to the dopants, the improved contact resistance with uniform silicide morphology was obtained. Therefore, CVD-Co/Ti/TiN contact silicide process can be regarded as the next generation contact silicidation process.

Formation of highly reliable Cu/low-k interconnects by using CVD Co barrier in dual damascene structures

CVD Co film was investigated as an alternative barrier layer to the conventional PVD TaN\Ta in V1\M2 structure for 32nm node. We improved via filling performance and upstream (V1ƒM2) electromigration (EM) lifetime by more than three times. Excellent step coverage of CVD barrier makes it possible to reduce the thickness of the barrier metal by 30% and to increase the volume of Cu in metal lines. RC delay also reduced with decrease in resistance. Since adhesion at the interface between the barrier-Co and Cu also is strong, migration of Cu atoms is dramatically slowed down. EM in the via is finally deterred due to absence of pre-existing voids, consequently lifetime increases. This CVD Co process is expected to be beneficial for the next technology generation beyond 20nm node.

Effect of a noble annealing system on nickel silicide formation

We have investigated the formation of NiSi dependence on three types of annealing systems: annealing systems-I, -II, and -III. The annealing system-I transfers heat by radiation from tungsten halogen lamps in a N2 atmosphere to the wafer and the annealing system-II by conduction from a heated hot plate in vacuum to the wafer. On the other hand, annealing system-III uses a combination of convective and gas phase conductive heat transfer in a N2 atmosphere for wafer heating. Smooth surface and interface morphologies and good electrical properties were obtained for NiSi layers formed using annealing system-III. The wafer heat transfer mechanism from the heat source to wafer is shown to influence the morphological and electrical properties of NiSi