Sug-Woo Jung

Investigation of Chemical Vapor Deposition (CVD)-Derived Cobalt Silicidation for the Improvement of Contact Resistance

The improved contact resistance was obtained by the new barrier metal scheme such as CVD-Co/Ti/TiN process in the level of about half of that from CVD-Ti/TiN process. And the mechanism of contact silicidation of CVD-Co/Ti/TiN was investigated. Because Co silicide may prohibit the Si diffusion into Ti silicide and Si recess during TiCl4-based CVD-Ti process, and the inertness of Co silicide to the dopants, the improved contact resistance with uniform silicide morphology was obtained. Therefore, CVD-Co/Ti/TiN contact silicide process can be regarded as the next generation contact silicidation process.

Soft error immune 0.46 /spl mu/m/sup 2/ SRAM cell with MIM node capacitor by 65 nm CMOS technology for ultra high speed SRAM

The smallest SRAM cell, 0.46 um/sup 2/, is realized by a single pitch cell layout, gate poly trim mask technique, 80 nm contact holes formed by polymer attaching process, and a 193 nm ArF lithography process. The MIM (metal-insulator-metal) node capacitor is developed and used for the first time in the SRAM cell to reduce the radiation induced soft error rate, dramatically. The high performance transistors are developed with a channel length of 70 nm, plasma nitrided 13 /spl Aring/ gate oxide, low thermal budget sidewall spacer, and CoSix.

Effect of a noble annealing system on nickel silicide formation

We have investigated the formation of NiSi dependence on three types of annealing systems: annealing systems-I, -II, and -III. The annealing system-I transfers heat by radiation from tungsten halogen lamps in a N2 atmosphere to the wafer and the annealing system-II by conduction from a heated hot plate in vacuum to the wafer. On the other hand, annealing system-III uses a combination of convective and gas phase conductive heat transfer in a N2 atmosphere for wafer heating. Smooth surface and interface morphologies and good electrical properties were obtained for NiSi layers formed using annealing system-III. The wafer heat transfer mechanism from the heat source to wafer is shown to influence the morphological and electrical properties of NiSi

Investigation of CVD-Co Silicidation for the Improvement of Contact Resistance

In present, TiCl4-based CVD-Ti/TiN process is widely used to make a TiSi2 ohmic layer in about sub-100nm contacts. But TiCl4 based CVD-Ti/TiN process has some problems such as reactivity of TiSi2 with dopant and rapidly increased contact resistance at small contact CDs. These problems of TiSi2 have limited the implementation and extension of the CVD-Ti./TiN barrier metal process. A novel barrier metal process has been needed for achieving low BL/n+ and BL/p+ contact resistances in the next generation devices with sub-100nm. One of the solutions for these problems is the change of ohmic material from TiSi2 to CoSi2 which has inert characteristics with the dopants for contact ohmic layer. Therefore, CVD-Co process can be a adequate alternative to CVD-Ti process in the development of next generation MOS devices. Recently, Kang et al. have reported that the usefulness of CVD-Co process using CCTBA precursor which has a good step coverage, and which can be also extended to the silicide in 110nm contacts for achieving low contact resistances. In this paper, the results of sub-100nm DC contact resistances with CVD-Co silicide are reported. we studied the reason of the degree of increase of Rc with decreasing contact size was lower with CVD-Co/Ti/TiN at small contacts compared to CVD-Ti/TiN. The mechanism responsible for Cobalt silicidation from CCTBA based CVD-Co in small DC was suggested by analysis of phase transformation and morphology of Co and Ti silicide.