Kiwon Choi

Power Delivery Network Design for 3D SIP Integrated over Silicon Interposer Platform

As mobile hand-held devices including mobile phone are required to provide multi-media services more and more, it is necessary that the various hardware including high speed memory, high capacity data storage device, and high performance logic processor are integrated into the limited volume, which results in high density 3D SIP. In this work, power delivery network for 3D SIP integrated on silicon interposer will be discussed. The silicon interposer used in 3D SIP includes integrated decoupling capacitor, which gives good power delivery performance.

A new efficient equivalent circuit extraction method for multi-port high speed package using multi-input multi-output transmission matrix and polynomial curve fitting

Modem high-speed integrated circuits for multi-gigabit applications require high-density packages with several hundred YO pins, which also require a wideband circuit model of package. Since a wideband model of a multi-port network is generally calculated by a full-wave field solver and given in the form of a scattering parameter, a SPICEcompatible circuit model must be extracted from a scattering matrix. We present the concrete maxtrix formulation for tranforming scattering parameter to transmission matrix for a ZN-port network . This transformation results in a new efficient equivalent circuit extraction method, which conveniently incorporates accurate electromagnetic models of an interconnecting structure including electronic package into a circuit simulator. By using this new exfraction method, we can easily determine the valid bandwidth of an equivalent circuit model .

Reliability of flip chip BGA package on organic substrate

In this paper various reliability issues of the flip chip package on organic substrate, such as the 1st level bump joint reliability, die cracking, underfill cracking, and 2nd level solder ball joint reliabilty, are primarily described. This paper discusses the reasons and resolutions of failures.

Set-level thermal management with package thermal design in digital TV application

Thermal resistance is the most important parameter in package selection of high power devices. However, lower thermal resistances means higher package cost, so it is not easy to adopt high cost package like cavity down packages or flip-chip packages just for the thermal characteristics. Therefore, set-level thermal management and optimal thermal guide should be done before selecting thermally enhanced packages because set-level thermal management can provide us various possibilities to get proper thermal budget. Moreover, set-level thermal management can be very powerful tool in case of digital TV application because its thermal environment is apparently different from JEDEC thermal standards (JESD51). This paper will introduce simulation methodology for optimal thermal design in set- level including package selection with experimental work in digital TV applications.

Upper/Lower Boundary Estimation of Package Interconnect Parasitics for Chip-Package Co-Design

In this paper, we introduce a new, highly accurate, package parasitics estimation technique (PME: package model estimator) that can simultaneously consider both on-chip and off-chip parasitic effects at the early stage of chip design. The performance of the proposed technique was verified by application to a substrate package designed for mass production. This paper mainly focuses on the estimation of electrical models of unrouted PCB traces in the early stage of package design by the use of the weighting factor (W) reflecting the irregular routability of a substrate design. It is clearly shown that the proposed estimation algorithm produces excellent results compared to the post-simulation models for simple as well as complicated package designs. The efficient chip-package co-design technique, which accounts for all necessary parasitic effects of the package, can accurately predict the upper and lower boundaries of the noise margin for worst cases

A Junction Temperature Reduction Technique for a Microprocessor Considering Temperature Coupled Leakage Power

Leakage power is emerging as a key challenge in IC design. Since leakage power has super-linear dependency on operating temperature, it becomes imperative to consider the thermal effects while optimizing leakage power. In this paper, an inter-simulation technique which accounts for leakage power and temperature variations is present. Integrating leakage model and coupled thermal-leakage simulations, the converged temperature and power distributions are achieved. In order to flatten the on chip temperature gradient, the revised floorplan design of a microprocessor is proposed. The on-chip temperature distributions are verified with measurement results using an infrared thermography method. The analysis results show that the realistic on-chip temperature distribution is a key for a precise estimation of leakage power. In addition, an important design implication is that the leakage power optimization problem has to be considered as a synthetic task considering logic organization, circuit parameters and chip floor plan.

Development of Junction Temperature Decision (JTD) Map for Thermal Design of Nano-scale Devices Considering Leakage Power

As semiconductor technology keeps scaling down, leakage power grows significantly due to the reduction in threshold voltage, channel length, and gate oxide thickness. As the junction temperature increases in nano-scale devices, leakage power increases drastically. This phenomenon motivates the processor and package designers to take into account thermal effects due to the large leakage power for highly reliable design of high-performance systems. In this paper, an analytical methodology for estimating the junction temperature and initial temperature range was provided to avoid diverging junction temperature status in nano-scale devices. For this purpose, junction temperature decision (JTD) map and initial temperature limit (ITL) map was newly introduced.

Thermal Characterization of Multi Stack Packages Using Linear Superposition Method

As the mobile products have been developed, many devices of various functions should be packaged into the limited space. Therefore, stacking multi-packages is needed for small form factor. Compared with discrete packages, multi stack packages (MSP) can provide better solutions for power saving, EMI reduction, max frequency up-grade in spite of its higher cost, low test yield, poor quality assurance, and more complicated manufacturing process. But, stacking many packages in confined space has raised concerns related to heat dissipation, which has become one of the most serious problems in the design of MSP. Accordingly, a method to obtain Tj for each chip from the power inputs is needed. This is quite significant at the MSP promotion and design stage, though the temperature value would be changed by system environment. In this paper, a new approach to determine the junction temperatures of the MSP is proposed. The average temperature of the chips was calculated by RSM, and the temperature difference from the average temperature was calculated by linear superposition. Using this approach, one can calculate device junction temperatures simply and accurately