Ewan Towie

Simulation Study of the Impact of Quantum Confinement on the Electrostatically Driven Performance of n-type Nanowire Transistors

In this paper, we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWTs) for application in advanced CMOS technologies. The 3-D drift-diffusion simulations based on the density gradient approach that has been calibrated with respect to the solution of the Schrödinger equation in 2-D cross sections along the direction of the transport are presented. The simulated NWTs have cross sections and dimensional characteristics representative of the transistors expected at a 7-nm CMOS technology. Different gate lengths, cross-sectional shapes, spacer thicknesses, and doping steepness were considered. We have studied the impact of the quantum corrections on the gate capacitance, mobile charge in the channel, drain-induced barrier lowering, and subthreshold slope. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also investigated. We have also estimated the optimal gate length for different NWT design conditions.

Impact of Precisely Positioned Dopants on the Performance of an Ultimate Silicon Nanowire Transistor: A Full Three-Dimensional NEGF Simulation Study

In this paper, we report the first systematic study of quantum transport simulation of the impact of precisely positioned dopants on the performance of ultimately scaled gate-all-around silicon nanowire transistors (NWTs) designed for digital circuit applications. Due to strong inhomogeneity of the selfconsistent electrostatic potential, a full 3-D real-space nonequilibrium Green function formalism is used. The simulations are carried out for an n-channel NWT with 2.2 × 2.2 nm2 cross section and 6-nm channel length, where the locations of the precisely arranged dopants in the source-drain extensions and in the channel region have been varied. The individual dopants act as localized scatters, and hence, impact of the electron transport is directly correlated to the position of the single dopants. As a result, a large variation in the ON-current and a modest variation of the subthreshold slope are observed in the ID-VG characteristics when comparing devices with microscopically different discrete dopant configurations. The variations of the current-voltage characteristics are analyzed with reference to the behavior of the transmission coefficients.

3D multi-subband ensemble Monte Carlo simulator of FinFETs and nanowire transistors

In this paper we present the development of a 3D Multi Subband Ensemble Monte Carlo (3DMSB-EMC) tool targeting the simulation of nanoscaled FinFETs and nanowire transistors. In order to deliver computational efficiency, we have developed a self-consistent framework that couples a MSB-EMC transport engine for a 1D electron gas with a 3DPoisson-2DSchrödinger solver. Here we use a FinFET with a physical channel length of 15nm as an example to demonstrate the applicability and highlight the benefits of the simulation framework. A comparison of the 3DMSB-EMC with Non-Equilibrium Greens Functions (NEGFs) in the ballistic limit is used to verify and validate our approach.

Predicting future technology performance

In this paper we highlight the important role of full-scale 3D Ensemble Monte Carlo (EMC) transport simulations in the performance analysis of contemporary and future decananometer MOSFETs. Considering both electron and hole transport in alternative device structures and materials we demonstrate that conventional drift diffusion (DD) simulations using standard mobility models fail to capture the non-equilibrium transport effects present in these devices, limiting their effectiveness in terms of performing predictive simulation of Si based FinFETs. We clearly demonstrate the capabilities and the power of EMC in evaluating the scaling potential and performance of FinFETs and quantum well transistors employing high mobility materials and the impact that additional scattering sources has on their performance.

Inverse Scaling Trends for Charge-Trapping-Induced Degradation of FinFETs Performance

In this paper, we investigate the impact of a single discrete charge trapped at the top oxide interface on the performance of scaled nMOS FinFET transistors. The charge-trapping-induced gate voltage shift is simulated as a function of the device scaling and for several regimes of conduction-from subthreshold to ON-state. Contrary to what is expected for planar MOSFETs, we show that the trap impact decreases with scaling down the FinFET size and the applied gate voltage. By comparing drift-diffusion with nonequilibrium Green functions simulations, we show that quantum effects in the charge distribution and transport can reduce or amplify the impact of discrete traps in simulation of reliability resilience of scaled FinFETs.

Impact of strain on the performance of Si nanowires transistors at the scaling limit: A 3D Monte Carlo/2D poisson schrodinger simulation study

In this work we investigate the correlation between channel strain and device performance in various n-type Si-NWTs. We establish a correlation between strain, gate length and cross-section dimension of the transistors. For the purpose of this paper we simulate Si NWTs with a <;110> channel orientation, four different ellipsoidal channel cross-sections and five gate lengths: 4nm, 6nm, 8nm, 10nm and 12nm. We have also analyzed the impact of strain on drain-induced barrier lowering (DIBL) and the subthreshold slope (SS). All simulations are based on a quantum mechanical description of the mobile charge distribution in the channel obtained from a 2D solution of the Schrödinger equation in multiple cross sections along the current path, which is mandatory for nanowires with such ultra-scale dimensions. The current transport along the channel is simulated using 3D Monte Carlo (MC) and drift-diffusion (DD) approaches.

Monte Carlo analysis of In 0.53 Ga 0.47 as Implant-Free Quantum-Well device performance

III–V nMOSFETs are promising candidates for n-channel high-performance transistors in CMOS in the sub-22 nm technology [1]. High electron mobility and low effective mass resulting in a very high injection velocity and low backscattering promise high device performance [2] at a low supply voltage. Various high-к dielectrics have been developed in order to meet the gate stack requirements of III–V MOSFETs [3]. However the introduction of III–V materials into CMOS requires transistor architectures that can take full advantage of the high mobility in the channel, simultaneously neutralising some of the potentially detrimental effects. Among such architectures, the Implant-Free Quantum-Well (IF-QW) transistor [4] offers interesting technological and performance advantages and tradeoffs (Fig. 1.). The IF-QW device features overgrown, heavily doped Source/Drain (S/D) contacts as a replacement of the conventional implanted junctions. The confinement of the carriers in the quantum well in combination with the p-type substrate doping below the channel provides excellent electrostatic integrity.

Remotely screened electron-impurity scattering model for nanoscale MOSFETs

The ionized impurities within the channel of nanoscale MOSFETs are shown to be strongly remotely screened by the close proximity of the highly doped, degenerate source and drain regions due to polarization charge effects. The position of the ionized impurity within the channel region controls the strength of the remote screening due to polarization charges induced in the source and drain, which increase heavily as the channel screening length exceeds the channel length. A remotely screened ionized impurity scattering potential is calculated based on an exact solution to Poissons equation for a model system. This scattering potential includes the polarization charge effects from the source and the drain which may contribute separately or in combination depending on the position of the ionized impurity and the channel screening length. A scattering model is developed based on a simplified form of this scattering potential that is suitable for use in Monte Carlo simulations. The resulting scattering model is analysed and is shown to increase the ionized impurity mobility in the channel by a noticeable amount.

Performance of vertically stacked horizontal Si nanowires transistors: A 3D Monte Carlo/2D Poisson Schrodinger simulation study

In this paper we present a simulation study of 5nm vertically stacked lateral nanowires transistor (NWTs). The study is based on calibration of drift-diffusion results against a Poisson-Schrodinger simulations for density-gradient quantum corrections, and against ensemble Monte Carlo simulations to calibrate carrier transport. As a result of these calibrated results, we have established a link between channel strain and the device performance. Additionally, we have compared the current flow in a single, double and triple vertically stacked lateral NWTs.

One-dimensional multi-subband Monte Carlo simulation of charge transport in Si nanowire transistors

In this paper, we employ a newly-developed one-dimensional multi-subband Monte Carlo (1DMSMC) simulation module to study electron transport in nanowire structures. The 1DMSMC simulation module is integrated into the GSS TCAD simulator GARAND coupling a MC electron trajectory simulation with a 3D Poisson-2D Schrödinger solver, and accounting for the modified acoustic phonon, optical phonon, and surface roughness scattering mechanisms. We apply the simulator to investigate the effect of the overlap factor, scattering mechanisms, material and geometrical properties on the mobility in silicon nanowire field-effect transistors (NWTs). This paper emphasizes the importance of using 1D models that include correctly quantum confinement and allow for a reliable prediction of the performance of NWTs at the scaling limits. Our simulator is a valuable tool for providing optimal designs for ultra-scaled NWTs, in terms of performance and reliability.