Gianluca Traversi

Impact of Lateral Isolation Oxides on Radiation-Induced Noise Degradation in CMOS Technologies in the 100-nm Regime

Degradation mechanisms associated to lateral isolation oxides are discussed to account for total ionizing dose effects on the noise performance of 90 nm and 130 nm CMOS devices and for their dependence on geometry and operating conditions. In NMOSFETs with a conventional open layout, after irradiation the parasitic transistor at the device edges turns on and contributes to the total device noise. The paper provides a model to help understanding the impact of this radiation-induced noise contribution on white and 1/f noise terms. The different behavior of NMOSFETs in the two examined technology nodes is analyzed in this framework, and design criteria to reduce noise degradation in irradiated devices are discussed.

Total ionizing dose effects on the noise performances of a 0.13 /spl mu/m CMOS technology

This paper presents a study of the ionizing radiation tolerance of 0.13 /spl mu/m CMOS transistors, in view of the application to the design of rad-hard analog integrated circuits. Static, signal and noise parameters of the devices were monitored before and after irradiation with /sup 60/Co /spl gamma/-rays at a 10 Mrad total ionizing dose. The effects on key parameters such as threshold voltage shift and 1/f noise are studied and compared with the behavior under irradiation of devices in previous CMOS generations.

Design Optimization of Charge Preamplifiers With CMOS Processes in the 100 nm Gate Length Regime

Low noise design of charge sensitive amplifiers in deep submicron CMOS technologies is discussed based on the experimental characterization of transistors belonging to a 130 nm and a 90 nm minimum channel length processes. After briefly examining the main preamplifier noise sources, residing in the input element, achievable resolution limits in charge measuring systems employing such technologies are discussed under different detector capacitance, processing time and power dissipation constraints. The equivalent noise charge (ENC) model adopted in this work takes into account the behavior of series 1/f noise as a function of the overdrive voltage in PMOS devices. Moreover, noise in the gate current, whose effects could be neglected in past CMOS technologies featuring larger gate oxide thickness, is shown to play a role in the optimization process, significantly affecting the preamplifier performance at long shaping times. The extent of this contribution, besides depending on the drain current in the input device, is also determined by its drain voltage, which therefore may become a critical parameter in the design of low noise analog blocks.

Noise Characterization of 130 nm and 90 nm CMOS Technologies for Analog Front-end Electronics

Deep-submicron complementary MOS processes have made the development of ASICs for HEP instrumentation possible. In the last few years CMOS commercial technologies of the quarter micron node have been extensively used in the design of the readout electronics for highly granular detection systems in the particle physics environment. IC designers are now moving to 130 nm CMOS technologies, or even to the next technology node, to implement readout integrated circuits for silicon strip and pixel detectors, in view of future HEP applications. In order to evaluate how scaling down of the device features affects their performances, continuous technology monitoring is mandatory. In this work the results of signal and noise measurements carried out on CMOS devices in 130 nm and 90 nm commercial processes are presented. Data obtained from the measurements provide a powerful tool to establish design criteria in nanoscale CMOS processes for detector front-ends and can be used to evaluate the resolution limits achievable for low-noise charge sensitive amplifiers in the 100-nm minimum feature size range.

Survey of noise performances and scaling effects in deep submicrometer CMOS devices from different foundries

Submicrometer CMOS technologies provide well-established solutions to the implementation of low-noise front-end electronics for a wide range of detector applications. Since commercial CMOS processes maintain a steady trend in device scaling, it is essential to monitor the impact of these technological advances on the noise parameters of the devices. In this paper we present the results of an extensive analysis carried out on CMOS transistors fabricated in 0.35, 0.25, and 0.18 mum technologies from different foundries. This allows us to evaluate the behavior of 1/f and channel thermal noise parameters with different gate oxide thickness and minimum channel length and to give an estimate of their process-to-process spread. The experimental analysis is focused on actual device operating conditions in monolithic detector readout systems. This means that moderate or weak inversion are often the only relevant regions for front-end devices. To account for different detector requirements, the noise behavior of devices with different geometries and input capacitance was investigated. The large set of data gathered from the measurements provides a powerful tool to model noise parameters and establish front-end design criteria in deep submicrometer CMOS processes

Design of Time Invariant Analog Front-End Circuits for Deep N-Well CMOS MAPS

This work is concerned with the design of time invariant analog circuits for processing the signals from deep N-well monolithic CMOS sensors. As compared to the three-transistor front-end typically used in imaging applications, the schemes proposed here, which were conceived to be included in a binary readout channel, lend themselves to pixel-level sparsified readout and are expected to be capable of managing the large flow of data anticipated for the future high luminosity colliding machines while obeying quite severe material budget requirements. Various solutions complying with different power dissipation and point resolution constraints have been implemented in a 130 nm CMOS technology, paying particular attention to equivalent noise charge and threshold dispersion performance. This paper intends to describe and compare the features of the different approaches by means of simulations, experimental results and theoretical analysis.

Survey of noise performances and scaling effects in deep submicron CMOS devices from different foundries

Submicron CMOS technologies provide well-established solutions to the implementation of low-noise front-end electronics for a wide range of detector applications. Since commercial CMOS processes maintain a steady trend in device scaling, it is essential to monitor the impact of these technological advances on the noise parameters of the devices. In this paper we present the results of an extensive analysis carried out on CMOS transistors fabricated in 0.35, 0.25 and 0.18 mum technologies from different foundries. This allows to evaluate the behavior of 1/f and channel thermal noise parameters with different gate oxide thickness and minimum channel length and to give an estimate of their process-to-process spread. The experimental analysis is focused on actual device operating conditions in monolithic detector readout systems. This means that moderate or weak inversion are often the only relevant regions for front-end devices. To account for different detector requirements, the noise behavior of devices with different geometries and input capacitance was investigated. The large set of data gathered from the measurements provides a powerful tool to model noise parameters and establish front-end design criteria in deep submicron CMOS processes.

Mechanisms of Noise Degradation in Low Power 65 nm CMOS Transistors Exposed to Ionizing Radiation

Experimental data provide insight into the mechanisms governing the impact of gate and lateral isolation dielectrics and of scaling-related technological advances on noise and its sensitivity to total ionizing dose effects in Low Power 65 nm CMOS devices. The behavior of the 1/f noise term is correlated with the effects on the drain current that irradiation brings along by turning on lateral parasitic transistors. A comparison with data from previous CMOS generations is carried out to assess the impact of process features on radiation-induced degradation effects.

TID Effects in Deep N-Well CMOS Monolithic Active Pixel Sensors

This paper is devoted to the study of total ionizing dose effects in deep N-well (DNW) CMOS monolithic active pixel sensors (MAPS) for particle tracking fabricated in a STMicroelectronics 130 nm process. DNW-MAPS samples were exposed to gamma-rays up to a final dose of 1100 krad(SiO2) and then subjected to a 100degC annealing cycle. Ionizing radiation tolerance was tested by monitoring the device noise properties and its response to charge injection through an external pulse generator throughout the irradiation and annealing campaign. The origins of performance degradation are discussed based on the results from radiation hardness characterization of single transistors belonging to the same CMOS technology and of test diodes reproducing the MAPS collecting electrode structure. Also circuit simulations have been performed to supply further evidence for the proposed degradation mechanisms.

Investigating Degradation Mechanisms in 130 nm and 90 nm Commercial CMOS Technologies Under Extreme Radiation Conditions

The purpose of this paper is to study the mechanisms underlying performance degradation in 130 nm and 90 nm commercial CMOS technologies exposed to high doses of ionizing radiation. The investigation has been mainly focused on their noise properties in view of applications to the design of low-noise, low-power analog circuits to be operated in harsh environment. Experimental data support the hypothesis that charge trapping in shallow trench isolation (STI), besides degrading the static characteristics of interdigitated NMOS transistors, also affects their noise performances in a substantial fashion. The model discussed in this paper, presented in a previous work focused on CMOS devices irradiated with a 10 Mrad(SiO2) gamma -ray dose, has been applied here also to transistors exposed to much higher (up to 100 Mrad(SiO2 )) doses of X-rays. Such a model is able to account for the extent of the observed noise degradation as a function of the device polarity, dimensions and operating point.