Massimo Manghisoni

Impact of Lateral Isolation Oxides on Radiation-Induced Noise Degradation in CMOS Technologies in the 100-nm Regime

Degradation mechanisms associated to lateral isolation oxides are discussed to account for total ionizing dose effects on the noise performance of 90 nm and 130 nm CMOS devices and for their dependence on geometry and operating conditions. In NMOSFETs with a conventional open layout, after irradiation the parasitic transistor at the device edges turns on and contributes to the total device noise. The paper provides a model to help understanding the impact of this radiation-induced noise contribution on white and 1/f noise terms. The different behavior of NMOSFETs in the two examined technology nodes is analyzed in this framework, and design criteria to reduce noise degradation in irradiated devices are discussed.

Radiation hardness perspectives for the design of analog detector readout circuits in the 0.18-/spl mu/m CMOS generation

This paper presents a study of the ionizing radiation tolerance of analog parameters of 0.18-/spl mu/m CMOS transistors, in view of the application to the design of front-end integrated circuits for detectors in high-energy physics experiments. Static, signal, and noise performances of devices with various gate dimensions were monitored before and after irradiation up to a 300-kGy(Si) total dose of /sup 60/Co /spl gamma/-rays. Different device biasing conditions under irradiation were used, and the relevant results are discussed. A comparison with previous CMOS generations is carried out to evaluate the impact of device scaling on the radiation sensitivity.

Total ionizing dose effects on the noise performances of a 0.13 /spl mu/m CMOS technology

This paper presents a study of the ionizing radiation tolerance of 0.13 /spl mu/m CMOS transistors, in view of the application to the design of rad-hard analog integrated circuits. Static, signal and noise parameters of the devices were monitored before and after irradiation with /sup 60/Co /spl gamma/-rays at a 10 Mrad total ionizing dose. The effects on key parameters such as threshold voltage shift and 1/f noise are studied and compared with the behavior under irradiation of devices in previous CMOS generations.

FSSR2, a self-triggered low noise readout chip for silicon strip detectors

The FSSR2 is the second release of the Fermilab Silicon Strip Readout Chip. The chip has been designed and fabricated in a 0.25 mum CMOS technology for high radiation tolerance. The first release, simply called the FSSR, was a prototype version with many different analog front-end configurations. The best solution was chosen for the FSSR2 chip to optimize the noise, according to criteria discussed in this paper. The FSSR2 has been designed for the silicon strip detectors of the BTeV experiment. The chip services 128 strips and provides address, time and magnitude information for all hits. Several programmable features are included in FSSR2, such as an internal pulser, a baseline restorer and a signal peaking time selectable among four values in the range between 65 ns and 125 ns. The circuit design and the performance of FSSR2 are discussed in this paper

Front-end electronics for pixel sensors

Abstract This paper discusses the criteria that underlie the design of front-end systems for pixel sensors of different types in a highly diversified fields of application. In the pixel front-end systems, low level analog signals coexist with digital activities and the design must comply with severe limitations in the area and in the power allotted to the single pixel cell. Noise and radiation hardness issues are of utmost importance in several applications. Some ways to arrive at a design which suits specific application requirements are discussed and the impact of the most advanced monolithic processes is evaluated.

Design Optimization of Charge Preamplifiers With CMOS Processes in the 100 nm Gate Length Regime

Low noise design of charge sensitive amplifiers in deep submicron CMOS technologies is discussed based on the experimental characterization of transistors belonging to a 130 nm and a 90 nm minimum channel length processes. After briefly examining the main preamplifier noise sources, residing in the input element, achievable resolution limits in charge measuring systems employing such technologies are discussed under different detector capacitance, processing time and power dissipation constraints. The equivalent noise charge (ENC) model adopted in this work takes into account the behavior of series 1/f noise as a function of the overdrive voltage in PMOS devices. Moreover, noise in the gate current, whose effects could be neglected in past CMOS technologies featuring larger gate oxide thickness, is shown to play a role in the optimization process, significantly affecting the preamplifier performance at long shaping times. The extent of this contribution, besides depending on the drain current in the input device, is also determined by its drain voltage, which therefore may become a critical parameter in the design of low noise analog blocks.

Noise Characterization of 130 nm and 90 nm CMOS Technologies for Analog Front-end Electronics

Deep-submicron complementary MOS processes have made the development of ASICs for HEP instrumentation possible. In the last few years CMOS commercial technologies of the quarter micron node have been extensively used in the design of the readout electronics for highly granular detection systems in the particle physics environment. IC designers are now moving to 130 nm CMOS technologies, or even to the next technology node, to implement readout integrated circuits for silicon strip and pixel detectors, in view of future HEP applications. In order to evaluate how scaling down of the device features affects their performances, continuous technology monitoring is mandatory. In this work the results of signal and noise measurements carried out on CMOS devices in 130 nm and 90 nm commercial processes are presented. Data obtained from the measurements provide a powerful tool to establish design criteria in nanoscale CMOS processes for detector front-ends and can be used to evaluate the resolution limits achievable for low-noise charge sensitive amplifiers in the 100-nm minimum feature size range.

Survey of noise performances and scaling effects in deep submicrometer CMOS devices from different foundries

Submicrometer CMOS technologies provide well-established solutions to the implementation of low-noise front-end electronics for a wide range of detector applications. Since commercial CMOS processes maintain a steady trend in device scaling, it is essential to monitor the impact of these technological advances on the noise parameters of the devices. In this paper we present the results of an extensive analysis carried out on CMOS transistors fabricated in 0.35, 0.25, and 0.18 mum technologies from different foundries. This allows us to evaluate the behavior of 1/f and channel thermal noise parameters with different gate oxide thickness and minimum channel length and to give an estimate of their process-to-process spread. The experimental analysis is focused on actual device operating conditions in monolithic detector readout systems. This means that moderate or weak inversion are often the only relevant regions for front-end devices. To account for different detector requirements, the noise behavior of devices with different geometries and input capacitance was investigated. The large set of data gathered from the measurements provides a powerful tool to model noise parameters and establish front-end design criteria in deep submicrometer CMOS processes

Design of Time Invariant Analog Front-End Circuits for Deep N-Well CMOS MAPS

This work is concerned with the design of time invariant analog circuits for processing the signals from deep N-well monolithic CMOS sensors. As compared to the three-transistor front-end typically used in imaging applications, the schemes proposed here, which were conceived to be included in a binary readout channel, lend themselves to pixel-level sparsified readout and are expected to be capable of managing the large flow of data anticipated for the future high luminosity colliding machines while obeying quite severe material budget requirements. Various solutions complying with different power dissipation and point resolution constraints have been implemented in a 130 nm CMOS technology, paying particular attention to equivalent noise charge and threshold dispersion performance. This paper intends to describe and compare the features of the different approaches by means of simulations, experimental results and theoretical analysis.

Survey of noise performances and scaling effects in deep submicron CMOS devices from different foundries

Submicron CMOS technologies provide well-established solutions to the implementation of low-noise front-end electronics for a wide range of detector applications. Since commercial CMOS processes maintain a steady trend in device scaling, it is essential to monitor the impact of these technological advances on the noise parameters of the devices. In this paper we present the results of an extensive analysis carried out on CMOS transistors fabricated in 0.35, 0.25 and 0.18 mum technologies from different foundries. This allows to evaluate the behavior of 1/f and channel thermal noise parameters with different gate oxide thickness and minimum channel length and to give an estimate of their process-to-process spread. The experimental analysis is focused on actual device operating conditions in monolithic detector readout systems. This means that moderate or weak inversion are often the only relevant regions for front-end devices. To account for different detector requirements, the noise behavior of devices with different geometries and input capacitance was investigated. The large set of data gathered from the measurements provides a powerful tool to model noise parameters and establish front-end design criteria in deep submicron CMOS processes.