Fang-Jun Leu

Reliability assessment of the 20 um pitch micro-joints within a 3DIC assembly under various environments

For the demands of multifunction, high density interconnection, high performance and integration of homogeneous or heterogeneous ICs, three dimensional IC (3DIC) packaging technologies by through silicon via (TSV) and microbump were widely studied recently. Intending to learn the reliability performance of Pb-free microjoints, 4 chips were interconnected with one Si interposer by Sn2.5Ag microbumps, sealed by a capillary underfill and then did the reliability assessment under different environments. The 4 chips have the same size of 4.6 mm by 4.6 mm by 100 um, and were assembled on one Si interposer with a dimension of 20 mm by 20 mm by 300 mm by a chip on wafer (CoW) bonder. There were more then 3000 microbumps on each chip and totally over 12,000 microbumps were on the Si interposer. The bump pitch and passivation opening of the test vehicle were 20 um and 6 um, respectively, an under bump metallization (UBM) layer of 5.0 um Cu / 3.0 um Ni was plating on Al trace and then Sn2.5Ag Pb-free solder bump with a thickness around 5.0 um was then deposited on the UBM layer. During bonding, the microjoints were formed at a peak temperature of 280°C, and the microgaps were then filled by a capillary underfill and cured at 150°C for 30 min. Subsequently, the assemblies were respectively inspected by an X-ray and a scanning acoustic microscope (SAM) to determine the quality of microjoints including bonding accuracy, formation of interconnections and the percentage of gas voids within the underfill. Afterwards, the test vehicles were baked at 125°C for 24 h and then stored under the test condition of 30°C / 60% RH for 192 h and finally reflowed at 260°C for 3 times to screen the samples for reliability tests, the SAM was again used to check whether the delamination defect was formed within the microgap. The reliability tests including temperature cycling test (TCT), thermal shock test (TST), high temperature storage test (HTS), pressure cooker test (PCT) and thermal humidity storage test (THST) were done according to the JEDEC standards. The results showed that the thermomechanical stress induced by TCT and TST damaged the assemblies, and the failure mode was also discussed in this investigation.

Characteristics of 600 V / 450 A IGBT module assembled by Ag sintering technology

Up to now, more than 180 countries including China, Japan, EU and others have signed the Kyoto Protocol, then “Energy-saving and Carbon reduction” becomes a popular slogan and an important mission to protect the environment and to pursue the national sustainability. Taiwanese government is pushing the R&D institutes like ITRI to develop the renewable energies and smart grid technologies, and is also making many environmental policies as well for driving the people to purchase the eco-products like electric car, hybrid car and household appliances to reach the goal of Carbon reduction, and the industries are also actively involved in the mass production of the key components such as high power IGBT modules for EV / HEV, intelligent power module (IPM) for air-conditioner, and MOSFET SiP modules for the power management of consumer electronics and hand-held machine tools. ITRI has already achieved a 600 V / 450 A IGBT module composed of IGBTs and freewheel diodes (FWD) for EV / HEV applications. Previously, a Pb-free solder perform with a thickness of 100 μm was adopted to attach 2 IGBTs and 2 FWDs on one Al2O3 direct bonded copper (DBC) substrate in a vacuum reflow oven, and 3 DBCs were then soldered on a Cu baseplate by a solder perform as well, by this structure, the junction temperature of the IGBT device is very close to 150°C and may deteriorate the long-term reliability. Therefore, a Ag paste sintering method was used to replace the conventional soldering process to improve the thermal dissipation and to lower the junction temperature. With an optimized process condition, a voidless die attaching joint was gained, and the die shear strength was as high as 27 MPa. Furthermore, a reduction of 22% of thermal resistance was measured by using Ag sintering, and the electrical performance of the newly developed power module was fully reported in this study.

The first MIT 600 V/450 a IGBT module for EV/HEV applications

Nowadays, more than 180 countries including China, Japan, EU and others have signed the Kyoto Protocol, then “Energy-saving and Carbon reduction” becomes a popular slogan and an important mission to protect the environment and to pursue the national sustainability. Taiwan government is making many environmental policies as well for driving the people to purchase the eco-products like electric car, hybrid car and household appliances to reach the goal of Carbon reduction, and the industries are also actively involved in the mass production of the key components such as high power IGBT modules for EV/HEV, intelligent power module (IPM) for air-conditioner, and MOSFET SiP modules for the power management of consumer electronics and hand-held machine tools. The first 600 V/450 A IGBT module for EV/HEV application developed by ITRI was announced in this work. The module was composed of IGBTs and freewheel diodes (FWD), firstly 2 IGBTs and 2 FWDs were attached on one Al2O3 direct bonded copper (DBC) substrate by a Pb-free solder perform with a thickness of 100 μm in a vacuum reflow oven, and 3 DBCs were then soldered on a Cu baseplate by a solder perform as well. After cleaning, a heavy Al wire was used to connect the devices and DBCs, and subsequently the housing was adhered to the Cu baseplate by an adhesive. Finally, a Si gel with a dielectric strength higher than 10 kV/mm was poured for insulation and then agglutinated by heating. The process conditions were optimized in this study, a die shear strength higher than 20 MPa was acquired after optimizing the reflow profile, and a design of experiments (DoEs) plan was executed to obtain a pull strength higher than 800 g for the heavy Al wire bonding. After temperature cycling for 1000 times, the loss of the strengths was less than 20%, and the long-term reliability of the power module was verified.

Processing characteristics and reliability of embedded DDR2 memory chips

As high-speed, high-density, and high-performance are the primary IC development targets, packaging technologies play a key role to bring out the best performance of those ICs. In this paper, an active component formed by an active chip embedded technology is developed for the package of a high speed DDR2 memory device. Embedding of semiconductor chips into an organic substrate provide a solution to miniaturize the size of the package. Moreover, stacking multiple layers of embedded components can allow an even higher capacity of devices and packaging density. In addition to wire bonding or w-BGA technologies, embedded package structure provides an alternative means to form redistribution circuits and electrical bonding pads. Meanwhile the electrical performance can be enhanced due to the wafer level package-like structure. Superior electrical performance is provided by forming shorter electrical path from chip pad to outer. In this study, a chip-in-substrate package (CiSP) with a real 50 um thick DDR2 memory IC is achieved using built-up technologies such as dielectric layer lamination, micro via drilling, and redistribution layer forming to implement the JEDEC-compliant DDR2 component. The PCB compatible process is a low-cost, high-yield, and versatile technology. Electrical performance similar to wafer level package and even better than wire bonding or w-BGA package can be achieved by adopting this proposed solution. The DDR2 component is assembled on a dual in-line memory module (DIMM) to study the feasibility and electrical performance of this developed package. Subsequent reliability test such as thermal cycle test (TCT) and thermal humidity storage test (THST) are examined. And electromigration (EM) of this test vehicle under high current density is simulated and tested.

Wafer level chip stacked module by embedded IC packaging technology

Wafer level chip stacked module by embedded IC packaging technology was studied in this paper. Wafers were treated to less than 50 mum thickness and then singulated. The prepared thin chips were stacked on to the base wafer and then embedded by dielectric layers (Ajinomoto build up film, ABF) lamination. Vias to both the pads on the analog chips and digital wafers were done by UV laser drilling process. After surface treatment and seed layer deposition, Cu plating process was adapted for the the via filling and traces patterning to form the interconnection between the chips and the component IO pads. Results of this study showed the benefits of the structure can provide more precise alignment and more reliable chip to wafer stacking without any voids or defects. Meanwhile, the presented wafer level process gives a much simple and cost effective package. By the described process integration, vertical chip stacked and embedded module within 300 mum thickness, excluding the solder ball, could be demonstrated. All the realization of this small size module will be revealed in detail. Severe reliability tests such as the 288degC solder dipping and 260degC level 3 pre-conditioning test were carried out to further clarify the component property. The corresponding failure analysis will be carried out to further clarify the key points of the whole demonstration.

Ag alloy wire bonding under electromigration test

Gold wire bonding has been widely utilized in semiconductor packaging industry for electrical connections. However, since the gold price is soaring in past ten years, the alternative materials, such as copper and silver, are the candidates to replace gold. The silver alloy wire has shown many advantages, including excellent electrical and thermal properties. However, not many studies have reported the electromigration (EM) induced failure of Ag alloy wire. This study employed silver alloy wires with 25.4μm diameter bonded on 4μm thick aluminum metallization of die pads to investigate their interfacial reaction and failure mechanism under current stressing of 8 × 104A/cm2 at ambient temperature of 175 °C. The resistance evolution of sample during current stressing and the microstructure of joint interface between silver alloy wire and Al bond pad were examined. The results show that the polarity effect of distinct surface morphology on ball bonds and of the different thickness of intermetallic compounds (IMCs) existed at the interface between the wires and Al pads. The corresponding mechanism and kinetic analysis for both void formation and IMCs growth will be proposed and discussed in the future. In addition, the ball pull test (BPT) was conducted before the electromigration test to understand the impact of various wire bonding parameters on mechanical properties.