Yu-Lan Lu

Characterization and reliability assessment of solder microbumps and assembly for 3D IC integration

In this investigation, Cu/Sn lead-free solder microbumps with 10μm pads on 20μm pitch are designed and fabricated. The chip size is 5mm × 5mm with thousands of microbumps. A daisy-chain feature is adopted for the characterization and reliability Assessment. After pattern trace formation, the microbump is fabricated on the trace by an electroplating technique. A suitable barrier/seed layer thickness is designed and applied to minimize the undercut due to wet etching but still achieve good plating uniformity. With the current process, the undercut is less than 1μm and the bump height variation is less than 10%. In addition, the shear test is adopted to characterize the bump strength, which exceeds the specification. Also, the Cu-Sn lead-free solder micro bumped chip is bonded on a Si wafer (chip-to-wafer or C2W bonding). Furthermore, the micro-gap between the bonded chips is filled with a special underfill. The shear strength of the bonded chips w/o underfill is measured and exceeds the specification. The bonding and filling integrity is further evaluated by open/short measurement, SAT analysis, and cross-section with SEM analysis. The stacked ICs are evaluated by reliability tests, including thermal cycling test (−55⇆125°C, dwell and ramp times = 15 min). Finally, ultra find-pitch (5μm pads on 10μm pitch) lead-free solder microbumping is explored.

Wafer Bumping, Assembly, and Reliability of Fine-Pitch Lead-Free Micro Solder Joints for 3-D IC Integration

In this investigation, Cu-Sn lead-free solder microbumps on 10-μm pads with a 20-μm pitch are designed and fabricated. The chip size is 5 × 5 mm with thousands of microbumps. A daisy-chain feature is adopted for the characterization and reliability assessment. After pattern trace formation, the microbump is fabricated on the trace by an electroplating technique. A suitable barrier/seed layer thickness is designed and applied to minimize the undercut due to wet etching but to still achieve good plating uniformity. With the current process, the undercut is less than 1 μm and the bump height variation is less than 10%. In addition, the shear test is adopted to characterize the bump strength, which exceeds the specification. Also, the Cu-Sn lead-free solder microbumped chip is bonded on an Si wafer using chip-to-wafer bonding technique. Furthermore, the microgap between the bonded chips is filled with a special underfill. The shear strength of the bonded chips without the underfill is measured and it exceeds the specification. The bonding and filling integrity is further evaluated by open/short measurement, scanning acoustic tomography analysis, and cross-section with scanning electron microscopy analysis. The stacked ICs are evaluated by reliability (thermal cycling) test (-55 to 125°C). Finally, ultrafine-pitch (5-μm pads on a 10-μm pitch) lead-free solder microbumping is explored.

Assembly of 3D chip stack with 30μm-pitch micro interconnects using novel arrayed-particles anisotropic conductive film

As the demands of functionality and performance for electronic products increase, three-dimensional chip stacking with high-density I/O has received much attention. For high density interconnections packaging, solder micro bumps are adopted extensively. However, its process temperature is high during chip stacking process. High bonding temperature would be easy to lead chip damage and chip warpage. For diminishing the thermal damage resulted from the high bonding temperature during chip stacking, we used the anisotropic conductive film as an intermediate layer to bond the chips. In this paper, a new type of ACF with Ni/Au-coated polymer arrayed particles was adopted for assembling a chip stack module with a micro bump pitch of 30μm. The reliability of the chip stack assembled by such novel material was evaluated and estimated also. The chip-to-chip stack module having more than 3000 I/Os with a pitch of 30μm was used as the test vehicle. The structure of Cu/Ni/Au micro bump was chosen and fabricated on both the silicon chip and substrate. The silicon chip was bonded onto the silicon substrate using the arrayed-particles ACF material after ACF lamination process. The optimized lamination conditions and the effects of bonding pressure and temperature were evaluated and determined by considering the particle deformation, electrical performance and adhesive flow phenomenon. After optimizing the lamination and bonding parameters, the reliability of the assembled C2C module was evaluated by Pre-condition test, TCT and THST. Cross-sectioned inspection of micro joints by scanning electron microscopy, observation of interface between adhesive and silicon by scanning acoustic tomography, and adhesion test of ACF film after bonding and precondition were conducted to determine the failure modes of the ACF joining. After precondition test, less than 15% of daisy-chain resistance variation was found. The ACF joints with stable electrical resistance could be obtained by such kind of novel material. Also, no any obvious ACF delamination could be observed. The adhesion strength did not show any degradation after precondition test. The reliability test results revealed that the assembled C2C module by the arrayed-particles ACF showed the acceptable reliability performance in TCT and THST. The results of failure analysis displayed that the connectivity of ACF joints was damaged by induced thermal stress coming from the mismatch of CTE between adhesive matrix and conductive particles during environmental testing. This study presented that the arrayed-particles anisotropic conductive film adopted had great potential and could be applied for the 3D chip stacking assembly with fine pitch interconnects.

Effect of metal finishing fabricated by electro and Electroless plating process on reliability performance of 30μm-pitch solder micro bump interconnection

Recently, three dimensional integration circuits technology has received much attention because of the demands of gradually increasing functionality and performance in microelectronic packaging for different types of electronic devices. For 3D chip stacking, high density interconnections are required in high-performance electronic products. Though the bumping process used could be either electroplating or electroless plating for fine pitch solder micro bumps, its process effect on the reliability performances of micro joints still needs to be clarified from the microstructural point of view, especially for the fine pitch solder micro bump interconnections. In this study, we discussed the effect of Ni/Au metal finishing fabricated by electro- and electroless plating on the reliability properties of 30μm-pitch lead-free solder micro interconnections. Palladium layer was chosen to evaluate its influence on the reliability response of fine-pitch solder micro joints with electroless Ni/Au surface finishing. The chip-to-chip test vehicle having more than 3000 solder micro bumps with a bump pitch of 30μm was used in this study. Two types of metal finishing, electroplating Ni/Au and electroless plating Ni/Pd/Au, were chosen and fabricated on the silicon carrier. In silicon carrier, the thickness of Ni layer was 2~3 μm while that of electroplating and electroless plating Au layer was 0.5μm and 0.02μm respectively. The thickness of Pd layer within the electroless Ni/Pd/Au structure was 0.05~0.1μm. The silicon chip with a solder micro bump structure of Cu/Ni/SnAg having a thickness of 5μm/3μm/5μm was used for C2C bonding. We adopted the fluxless thermocompression process for both types of micro joints and then the chip stack was assembled by capillary-type underfill. Temperature cycling test (TCT) and electromigration test (EM) were conducted to assess the effect of metal finishing on the reliability properties of those solder micro bump interconnections. The reliability results revealed that the thickness of Au layer would apparently influence the microstructure evolution within the solder micro bump interconnection after bonding process though the micro joints with thick Au layer could pass the 1000 cycles TCT. The micro joints with complicated interface reaction resulted from the thicker Au layer might lead a negative effect on the long-term reliability properties while the Pd layer would enhance the wetting ability of solder micro bump during joining. The results of EM reliability test displayed that both types of the micro joints had excellent electromigration resistance under the testing condition of 0.08A/150°C. The activated IMC growth within the micro joint during EM testing was the major reason for this superior property. This investigated completely presented the effect of metal finishing by electro- and electroless bumping processes on the reliability properties of fine pitch solder micro bump joints.

The development of high through-put micro-bump-bonded process with non-conductive paste (NCP)

In this study, various micro-bump-bonded structures with TCB + NCP processes were evaluated and developed. A commercial available snap-cure NCP material was applied for the joining processes study. Three types of micro bumps, Cu/Ni/Sn2.5Ag, Cu/Sn2.5Ag and Cu/Ni/Au- were fabricated and bonded to achieve joint structures of Cu/Ni/Sn2.5Ag/Ni/Cu, Cu/Ni/Sn2.5Ag/Au/Ni/Cu and Cu/Sn2.5Ag/Au/Ni/Cu. Moreover, the filler trapped and void issues which associated with the TCB+NCP process were also investigated. After the evaluation, the reliability test such as moisture sensitivity test level 3 (MSL 3), temperature cycling test (TCT) and high temperature Storage (HTS) were conducted to the bonded samples. Hereafter, the failure modes with the mentioned issues were analyzed and discussed. Based on the experimental and reliability results, the optimized TCB + NCP processes with various micro-bump-bonded structures can be established. The joints electrical and reliability performance associated with the failure mode were investigated and analyzed. Finally, the characteristics of each joint connection were defined.

Reliability assessment of the 20 um pitch micro-joints within a 3DIC assembly under various environments

For the demands of multifunction, high density interconnection, high performance and integration of homogeneous or heterogeneous ICs, three dimensional IC (3DIC) packaging technologies by through silicon via (TSV) and microbump were widely studied recently. Intending to learn the reliability performance of Pb-free microjoints, 4 chips were interconnected with one Si interposer by Sn2.5Ag microbumps, sealed by a capillary underfill and then did the reliability assessment under different environments. The 4 chips have the same size of 4.6 mm by 4.6 mm by 100 um, and were assembled on one Si interposer with a dimension of 20 mm by 20 mm by 300 mm by a chip on wafer (CoW) bonder. There were more then 3000 microbumps on each chip and totally over 12,000 microbumps were on the Si interposer. The bump pitch and passivation opening of the test vehicle were 20 um and 6 um, respectively, an under bump metallization (UBM) layer of 5.0 um Cu / 3.0 um Ni was plating on Al trace and then Sn2.5Ag Pb-free solder bump with a thickness around 5.0 um was then deposited on the UBM layer. During bonding, the microjoints were formed at a peak temperature of 280°C, and the microgaps were then filled by a capillary underfill and cured at 150°C for 30 min. Subsequently, the assemblies were respectively inspected by an X-ray and a scanning acoustic microscope (SAM) to determine the quality of microjoints including bonding accuracy, formation of interconnections and the percentage of gas voids within the underfill. Afterwards, the test vehicles were baked at 125°C for 24 h and then stored under the test condition of 30°C / 60% RH for 192 h and finally reflowed at 260°C for 3 times to screen the samples for reliability tests, the SAM was again used to check whether the delamination defect was formed within the microgap. The reliability tests including temperature cycling test (TCT), thermal shock test (TST), high temperature storage test (HTS), pressure cooker test (PCT) and thermal humidity storage test (THST) were done according to the JEDEC standards. The results showed that the thermomechanical stress induced by TCT and TST damaged the assemblies, and the failure mode was also discussed in this investigation.

The first MIT 600 V/450 a IGBT module for EV/HEV applications

Nowadays, more than 180 countries including China, Japan, EU and others have signed the Kyoto Protocol, then “Energy-saving and Carbon reduction” becomes a popular slogan and an important mission to protect the environment and to pursue the national sustainability. Taiwan government is making many environmental policies as well for driving the people to purchase the eco-products like electric car, hybrid car and household appliances to reach the goal of Carbon reduction, and the industries are also actively involved in the mass production of the key components such as high power IGBT modules for EV/HEV, intelligent power module (IPM) for air-conditioner, and MOSFET SiP modules for the power management of consumer electronics and hand-held machine tools. The first 600 V/450 A IGBT module for EV/HEV application developed by ITRI was announced in this work. The module was composed of IGBTs and freewheel diodes (FWD), firstly 2 IGBTs and 2 FWDs were attached on one Al2O3 direct bonded copper (DBC) substrate by a Pb-free solder perform with a thickness of 100 μm in a vacuum reflow oven, and 3 DBCs were then soldered on a Cu baseplate by a solder perform as well. After cleaning, a heavy Al wire was used to connect the devices and DBCs, and subsequently the housing was adhered to the Cu baseplate by an adhesive. Finally, a Si gel with a dielectric strength higher than 10 kV/mm was poured for insulation and then agglutinated by heating. The process conditions were optimized in this study, a die shear strength higher than 20 MPa was acquired after optimizing the reflow profile, and a design of experiments (DoEs) plan was executed to obtain a pull strength higher than 800 g for the heavy Al wire bonding. After temperature cycling for 1000 times, the loss of the strengths was less than 20%, and the long-term reliability of the power module was verified.

Assembly and reliability assessment of 50µm-thick chip stacking by wafer-level underfill film

In order to meet the demands of high-performance, high-speed, small form factor and multi-function integration in portable electronic products, the development of packaging technology now trends toward system-in-package (SiP) technology. Three-dimension (3D) integrated circuit technology provides a way to integrate complex micro systems through vertical interconnections among individual devices/chips. For the multi-chip stacking with fine gap and fine pitch solder micro bump interconnection, the dispensing of capillary underfill presents a major limitation in term of process time and process ability during assembly process. In this study, for realizing the multi-chip stacking, we developed a simplified assembly process by wafer-level underfill (WLUF). The WLUF film was laminated on 8” chip wafer with a thickness of 50μm. The chosen solder micro bump structure was Cu/Ni/Sn2.5Ag with a pitch of 30μm. After wafer dicing, the chip with WLUF was assembled on the substrate chip having the same micro bump structure. The optimized bonding parameters in such assembly process were also determined. The experimental results revealed that a robust joining and no voids formed between bonding interface could be achieved by this simplified assembly process. The results of reliability test showed that all samples could pass LV-3 pre-condition test. The failure percentage was about 10% under 1000 cycles of TCT where the failure mode was the cracks of micro joints and Al pad. The failure percentage was about 52% under 1000 hours of THST where the failure mode was crack of micro joints. All samples could pass the Un-biased HAST test. We also evaluated the feasibility of multi-thin-chip stacking by WLUF film. The experimental results showed that the first-layer micro joints raised 2% increase in contact resistance and the thickness of IMC layer increased 1μm thick only after four-layer chip stacking process. These experimental results displayed that the WLUF material exhibited a highly applied potential for multi-chip assembly process.

Evaluation of fine-pitch chip-to-chip interconnects using ACF material with arrayed particles

As the demands for high density 3DIC stacking increase, a fine-pitch chip-to-chip interconnects is becoming imperative. In conventional flip-chip technology, anisotropic conductive film (ACF) has been used in place of solder and underfill for chip attachment to substrates in some applications, because it provides many advantages. Generally speaking, ACF consists of an adhesive polymer matrix with randomly dispersed conductive particles, which establish the electrical contacts between the interconnections. In this paper, a new type of ACF with Ni/Au-coated polymer arrayed particles in the bottom layer of the film was prepared. The 30μm-pitch chip-to-chip (C2C) bonding technology was presented and the chip with 3264 I/Os was bonded onto the substrate using the ACF material. After ACF lamination process, conductive particles capture rate and attach status were calculated and observed from the optical microscope (OM). Therefore, the ACF lamination condition was determined. After bonding process, the effects of bonding pressure and bonding temperature were discussed by considering particle deformation, electrical performance and adhesive flow status. After optimizing the lamination and bonding parameters, the reliability of C2C was evaluated by precondition test (125°C/24hrs backing, 30°C/60%RH/178hrs soaking, and 3times/265°C reflow). Cross-sectioned inspection of ACF joints by Scanning electron microscopy (SEM), the interface between adhesive and silicon observed by Scanning Acoustic Tomography (SAT), and adhesion strength test of ACF film after bonding and precondition were conducted to determine the failure modes. Moreover, after precondition test, the variation of near 70% of the C2C daisy chain resistance was found less than 15%. The stable electrical resistance and high reliability of ACF joints could be obtained. On the other hand, no any obvious delamination or failed joints could be observed within failure samples by SEM or SAT. Otherwise, the adhesion strength measured by shear test did not show any relations after the precondition test. We assumed that during the reflow process the entrapped adhesive matrix expanded much more than the conductive particles because of its higher coefficient of thermal expansion (CTE). Thus, induced thermal stress would separate the ACF joints and decrease the contact area of the conductive path.