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Analysis and design of amplifiers and comparators in CMOS 0.35 μm technology

Abstract Design techniques and CAD tools for digital systems are advancing rapidly at decreasing cost, while CMOS analog circuit design is related mostly with the individual experience and background of the designer. Therefore, the design of an analog circuit depends on several factors such as a reliable design methodology, good modeling and technology characterization. Most of this work focuses on the analysis of several analog circuits, including their functionality, using different design methodologies. Initially the determination of two key design parameters (slope factor n and early voltage VA) and the gm/ID characteristics were derived from simulations. Then, the analysis and design of three diferent analog circuits are presented. A comparison is made between two design methodology applied to an analog amplifier design. The first one is a conventional approach where transistors are in saturation. The second one is based on the gm/ID characteristic, that allows a unified synthesis methodology in all regions of operation of the transistor. The analog modules for comparison and continuous filtering, that find vast applications today, are then analyzed and designed with the parameters and methodology proposed.

A tool for automatic design of analog circuits based on gm/I/sub D/ methodology

The goal of this paper is to present a transistor optimization methodology for analog integrated CMOS circuits, based on the physics-based gm/ID characteristics provided by the ACM compact MOS model. This methodology is implemented in a design tool, exploiting all the design space with the use of simulated annealing optimization process. A single technology dependent curve and accurate expressions for transconductance and current in all operations regions are integrated in the methodology, providing solutions close to the optimum. The advantage of constraining the optimization within a power budget is of great importance for low-power applications. As an example, we show the optimization results obtained for the design of a folded-cascode operational amplifier and a comparison with a typical hand-made design procedure

A 1.4GHz Upconversion Mixer Design Using the g m /ID Method Suitable for a Multi-Band Analog Interface

This paper addresses the analysis and design of an upconversion mixer suitable for a multi-band analog interface for CMOS SOCs. This block must relocate an input signal from 3 different frequency bands (FM, VHF/UHF and CDMA/GSM) to a fixed IF frequency of 1.4 GHz. The mixer architecture is based on a Gilbert Cell and multi-tanh linearization technique, providing the required gain and linearity for different input frequencies. The mixer was designed in 0.18 mum CMOS process using the gm/ID design method. A 5bB gain, 12dB noise figure, and 1.5dBm IIP3 were obtained under different input frequencies.

A low-power RF/analog front-end architecture for LF passive RFID tags with dynamic power sensing

This paper presents a low power, low voltage RF/analog front-end architecture for LF RFID tags with a dynamic power sensing scheme. The front-end converts the incoming RF power into DC using a system that adjusts its performance according to the available RF power. The power sensing scheme, composed by a feedback system that “regulates” the RF clamp stage, improves the incoming available power to the system. All building blocks together with the RF air link and antenna interface were modeled using digital and electrical signals with high abstraction level, validating the architecture. Part of the proposed AFE architecture was silicon proven in a preliminary CMOS 0.18μm process test chip. This preliminary part includes the regulation stages and part of the RF section. It shows excellent results for a maximum of 3μA DC current consumption, over a wide range of input RF power.

A /spl Sigma//spl Delta/ A/D converter insensitive to SEU effects

This paper discusses a /spl Sigma//spl Delta/ A/D converter insensitive to SEU effects. We concentrated our first study in the analog part of the converter, proving that it is inherently immune to SEU. Afterwards, we studied several implementations of digital filters in order to minimize the cost of protecting the digital part against radiation effects. The use of the /spl delta/-operator allows a significant reduction on the area to be protected, while maintaining converter performance. The obtained simulation results showed that the /spl Sigma//spl Delta/ architecture provides excellent possibilities to build SEU immune AD converters.

Low-frequency passive RFID systems implementation in CMOS technology: design considerations and tradeoffs

Radio Frequency Identification (RFID) systems are widely used in a variety of tracking, security and tagging applications. Passive low-frequency (LF) RFID systems have a large installed base, mostly used for animal tagging and supply chain applications. Passive RFID tags generate their power from the incoming signal; therefore, they do not require a power source. Accordingly, minimizing the power consumption and the implementation area are usually the main design considerations. This paper presents a complete analysis on designing a passive LF RFID tag in CMOS process. A complete architecture for a LF passive RFID tag is presented and analyzed, together with a brief discussion of its main building blocks such as rectifier, voltage clamps, modulator, voltage regulator and voltage/current references. The IC was fabricated in 0.6µm CMOS process. The tag system uses a carrier frequency of 134.2kHz, 128bit one-time programmable memory, DBP codification and ASK modulation in the reverse link (tag to reader). Measurement results are given.

Track-and-Latch Comparator Design Using Associations of MOS Transistors and Characterization

This paper addresses the design of a track-and-latch switched analog comparator in a pre-diffused array of digital - i.e. minimum length - transistors. The mapping of each original single transistor of the circuit into an equivalent trapezoidal association of digital transistors (TAT) is analyzed. This analog module was analyzed, designed and prototyped in AMS 0.35 mum CMOS technology. Experimental results are presented, in order to validate the methodology. The comparator has a sensibility of 184 mV, maximum frequency of 18 MHz and a current consumption of 288 muA.

Analog IC modules design using trapezoidal association of MOS transistors in 0.35 /spl mu/m technology

This works addresses how analog modules can be designed in a pre-diffused array of digital - i.e. minimum length - transistors. The mapping of each original single transistor of the circuit into an equivalent trapezoidal association of digital transistors (TAT) is analyzed. Three methodologies for the calculation of the equivalent TAT are presented: a linear resistor, a current model and a small-signal equivalent array approximation. These methods are applied to two IC modules designed with TAT associations in 0.35 /spl mu/m technology to show the effect of the single-to-TAT conversions and to compare the conventional and the TAT design: a two-stage Miller operational amplifier and a track-and-latch switched analog comparator. The results are compared to the performance of the single-transistor designs, showing that minimum-length digital transistors can be properly arranged to obtain reasonable specifications for middle performance analog circuits. The advantages of the digital array are the reduced prototype time. The layout design of the TAT associations and of the full modules were done with LIT, an interactive layout tool.

Low-Power/Low-Voltage analog front-end for LF passive RFID tag systems

Radio Frequency Identification (RFID) systems are widely used in a variety of tracking, security and tagging applications. In this context, passive low-frequency (LF) RFID systems have a large installed base, mostly used for animal tagging and supply chain applications. This paper presents a Low-Power/Low-Voltage analog front-end architecture (AFE) for such RFID systems, discussing the design and technology issues related with standard deep-submicron CMOS processes. The AFE converts the incoming AC power (134.2kHz) into DC power (1.2V) and internal references (570mV and 5nA) using low power design techniques in order to increase overall performance. An improved rectifier structure was designed using a half-wave voltage doubler topology with self-bias feedback, providing efficient rectification. A shunt regulator stage was proposed as a fundamental part of the AFE architecture, since it keeps the rectified voltage at 3V and generates the signal for demodulation for all power levels and process variations. Finally, a low-power/low-voltage PMU architecture was designed, containing a new reference voltage approach based on two NMOS transistors with different Vts consuming 170nA (startup circuit included); a 5nA reference current based in SCM (Self Cascode Mosfet) structures; and a dual-mode capacitor-less voltage regulator consuming 400nA. In order to increase the yield of the system, the VI reference block passed through a yield optimization using the tool WiCkeD, which showed a block yield increase of 71.66%.

A band-pass Gm-C Filter design based on gm/ID methodology and characterization

This paper addresses the design of continuous-time CMOS Band-pass Gm-C Filter using a design methodology based on the gm/ID transistor characteristics. This analog module was analyzed, designed and prototyped in AMS 0.35μm CMOS technology. Experimental results are presented, in order to validate the methodology. The filter has a pass-band central frequency of about 5MHz (with a small tuning range), quality factor of 25 and a current consumption of 263μA.