Franco Stellari

New formulas of interconnect capacitances based on results of conformal mapping method

The work presents new formulas for the capacitances of the most common two-dimensional (2-D) interconnect structures. The results have been obtained by using a physically-based approach: each geometry has been divided into elementary components studied rigorously with the conformal mapping method. The capacitances of structures composed by one, two, or three lines on a ground plane are then written as a weighted sum of such elements. Since the elementary terms already account for the correct geometrical dependencies, very few numerical simulations have been required to tailor the formulas, attaining an accuracy higher than previously known results, over a wide range of the geometrical parameters of the lines.

CMOS circuit testing via time-resolved luminescence measurements and simulations

The continuous trend in modern CMOS technology toward smaller devices and faster clock frequency is challenging the picosecond imaging circuit analysis technique. In this paper we discuss the role of the single-photon avalanche diode with very sharp time resolution in testing CMOS circuits. Thanks to the 30 ps-time resolution, innovative measurements regarding delays and jitter are presented, along with a case study. A compact model of the luminescence is also proposed and used to compare on-chip electrical signals with optical waveforms.

A novel scan chain diagnostics technique based on light emission from leakage current

Scan chain diagnostics have become more important than ever due to the increasing complexity of VLSI designs, as more and more scan latches/flip-flops are utilized in designs, especially in microprocessors. At the same time, the off-state leakage current of CMOS technology grows exponentially from one generation to the next one. This fact imposes a big challenge on the chip design, packaging, cooling, etc. However, innovative applications, based on the detection of light emission due to off-state leakage current (LEOSLC) have been developed for testing and diagnosing modern VLSI circuits. We show that LEOSLC can be used to effectively debug, diagnose, and localize defects in a broken scan chain.

Testing and diagnostics of CMOS circuits using light emission from off-state leakage current

In recent years, innovative applications based on the detection of emission sources such as the light emission from off-state leakage current (LEOSLC) of CMOS transistors have been developed for testing and diagnosing modern ultralarge-scale integration circuits. In this paper, we show that LEOSLC can be used to effectively debug circuits, localize defects with a quick turn around time, read the logic state of gates, and extract the internal voltage drop of power distribution grids among others.

High-speed CMOS circuit testing by 50 ps time-resolved luminescence measurements

Noninvasive characterization of CMOS ring oscillators with 50 ps resolution is obtained by exploiting the broad-band infrared emission from switching transistors. A fast silicon single-photon avalanche-diode (SPAD) is used to attain high sensitivity and time resolution. Switching transitions of both nand p-channel MOSFETs are measured and the main features in the circuit operation are characterized. Systematic variations and increased jitter of switching transitions due to phase noise are accurately measured.

Model-based guidelines to suppress cable discharge event (CDE) induced latchup in CMOS ICs

An analytical model has been developed to provide physical design guidelines to suppress CDE-induced latchup in CMOS ICs. The design guidelines implemented in two test chips in IBMs 130nm technology successfully suppressed latchup against transient pulses of up to 6A peak current and against DC current pulses (EIA/JESD 78 test) of +/- 400mA.

Transmission line pulse picosecond imaging circuit analysis methodology for evaluation of ESD and latchup

This paper will demonstrate the synthesis of the high current pulse source method (e.g. used in transmission line pulse (TLP) systems) and the Picosecond Imaging Circuit Analysis (PICA) tool for the evaluation. of electrostatic discharge (ESD) and latchup phenomenon. In this fashion, the evolution of ESD and latchup can be evaluated in semiconductor devices, and in peripheral circuits at a wafer level or product level. The methodology described in this publication allows for visualization of ESD and latchup, events (e.g. animation in a picosecond time regime). The synthesis of the transmission line pulse (TLP) method and the PICA method allows for the extension of the ESD TLP methodology to terminal currents and spatial and time domain analysis for electrical characterization and reliability analysis, and the high current pulsed source extends the utilization of the PICA methodology for failure analysis on wafer and chip levels.

Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor

We propose a novel ultralow-power, high-sensitivity, bias-free sub-threshold process variation sensor for monitoring the random variations in the threshold voltage. The proposed sensor characterizes the threshold voltage mismatch between closely spaced, supposedly identical transistors using the exponential current-voltage relationship of sub-threshold operation. The sensitivity of the proposed sensor is 2.3× better than the previous sensor reported in the literature which utilizes above-threshold operation. To further improve the sensitivity of the proposed sensor, an amplifier stage working in the sub-threshold region is designed. This enables 4× additional increase in sensitivity. A test-chip containing an array of 128 PMOS and 128 NMOS devices has been fabricated in 65-nm bulk CMOS process technology. A total of 28 dies across the wafer have been fully characterized and the random threshold voltage variations are reported here.

MARVEL — Malicious alteration recognition and verification by emission of light

This paper presents a new technique for detecting chip alterations using intrinsic light emission in combination with electrical test. The key idea of this method is based on the fact that any active device emits infrared light emission when it is powered on. High sensitivity photon detectors can be employed to capture the weak emission while the chip under test is powered on and electric stimuli are applied to it. In particular, two main families of electrical test modes, static and dynamic, can be applied. Positive results of the application of this methodology as well as key challenges will be discussed in the paper, including spatial resolution, imaging processing, data interpretation, etc.

Operational amplifier based test structure for transistor threshold voltage variation

A new test structure has been developed, which is comprised of MOSFET arrays and an on-chip operational amplifier feedback loop for measuring threshold voltage variation. The test structure also includes an on-chip clock generator and address decoders to scan through the arrays. It can be used in an inline test environment to provide rapid assessment of Vt variation for technology development and chip manufacturing. Hardware results in a 65 nm technology are presented.