François Boedt

Internal Dissolution of Buried Oxide in SOI Wafers

High temperature anneal of SOI wafers in oxygen-free atmosphere results in internal buried oxide dissolution and top Si layer etching. Dissolution rate is determined by interstitial oxygen diffusion through the top Si layer and evaporation from the top Si surface in the form of SiO. It has been observed that kinetics of the process follows linear-parabolic law. Simple thermodynamic model is proposed, which explains observed dependences on temperature and top Si layer thickness.

SOI substrate readiness for 22/20 nm and for fully depleted planar device architectures

Fully depleted (FD) MOSFET architecture for sub-32 nm technology node requires a new SOI substrate fabrication to meet all the stringent specifications imposed by a FD device. Ultra Thin SOI (UTSOI) targets planar device architectures, stressing specifications for thickness uniformity. Also Ultra Thin Burried Oxyde (UTBOx) offers additional benefits such as the application of back bias, for example enhancing device stability or threshold voltage tuning. In this paper, we discuss the Smart CutTM technology capability for both UTSOI and UTBOx substrate design with the quality and specifications that meet the future FD technology requirements.

Excellent silicon thickness uniformity on Ultra-Thin SOI for controlling Vt variation of FDSOI

Thickness uniformity of the Ultra Thin SOI (UTSOI) substrates is one of the key criteria to control Vt variation of the planar FDSOI devices. We present an evolutionary approach to SmartCutTM technology which already allows achieving a maximum total SOI layer thickness variation of less than ± 10 Å on preproduction volume. Total thickness variation of ± 5 Å is targeted.

Reliability study in capacitor less 1T-RAM cells on SOI

We have shown that careful optimization of the write conditions is needed in order to achieve the stringent endurance spec of 1016 cycles for 1T-RAM cells without compromising the sense margin and retention. The degradation seen during cycling of the cells can be attributed to the creation of interface states and carrier trapping at either the source (“0”) or drain side (“1”). Overall reduction of the biases, especially VD, will have a beneficial effect on the endurance behavior.