Francois Rivet

A Disruptive Receiver Architecture Dedicated to Software-Defined Radio

The next generation of mobile terminals is faced with the emergence of the software-defined radio (SDR) concept. The communication devices tend to provide various wireless services through a multi-functional, multi-mode and multi-standard terminal. The SDR concept aims at designing a re-configurable radio architecture accepting all cellular or noncellular standards working in the 0-5-GHz frequency range. Some technical challenges have to be solved in order to address this concept. Working in the digital domain may be a solution but the analog-to-digital conversion cannot be done at Radio Frequencies, at an acceptable resolution and at an acceptable level of power consumption. The idea proposed here was to interface an analog pre-processing circuit between the antenna and a digital signal processor to pre-condition the RF signal. It uses the principle of a fast Fourier transform to carry out basic functions with high accuracy in a low-cost technology like CMOS. This paper presents the design and the behavioral simulations of this analog discrete-time device which gives the hardware flexibility required for a cognitive radio component.

The Experimental Demonstration of a SASP-Based Full Software Radio Receiver

Many technological bottlenecks prevent from realizing a software radio (SR) mobile terminal. The old way of building radio architectures is now over because a single handled terminal has to address various communication standards. This paper exposes a SR receiver: a sampled analog signal processor (SASP) is designed to perform downconversion and channel presorting. The idea is to process analog voltage samples in order to recover in baseband any RF signal emitted from 0 to 5 GHz. An analog fast Fourier transform achieves both frequency shifting and filtering. An experimental demonstrator of the SASP using 65 nm CMOS technology from STMicroelectronics is here presented and measured. It validates the concept of a new SR receiver with the design of a demonstrator which runs at 1.2 GHz consuming 389 mW.

A Disruptive Software-Defined Radio Receiver Architecture Based on Sampled Analog Signal Processing

Software defined radio (SDR) aims at bringing digital treatment chip closer to the antenna in a mobile terminal architecture. The main goal is to create a re-configurable radio architecture accepting all the cellular or non-cellular standards working in the 0-5 GHz frequency range. But, in this environment, the analog to digital conversion and the digital operations face issues like power supply and processing speed. The idea is to interface a preprocessing circuit between the antenna and a digital signal processor (DSP) to pre-condition the RF signal. This paper presents the design of an analog discrete-time device located between antenna and a DSP in standard radio architecture. It uses the principle of the discrete Fourier transform (DFT) to reduce the frequency of the DSP-input-signal treatment to fulfil the SDR purpose. It has been validated through system level simulation.

The first experimental demonstration of a SASP-based full Software Radio receiver

This paper presents the principles of a Sampled Analog Signal Processor (SASP) dedicated to Software Radio mobile device. Many technological bottlenecks are to be overcome. The idea is to design a discrete analog signal processor to challenge theses bottlenecks. The main issue associated with the A/D conversion is thus avoided. The SASP aims to select a spectral envelope of a RF signal among all RF signals. To reach that target, the SASP processed analogically the RF input signal spectrum thanks to an analog Discrete Fourier Transform (DFT). Once the spectrum processed, only the voltage samples representing the signal envelope to be treated are converted into digital. The selection of few voltage samples among thousands others replaces the classical mixing and filtering operations. It dramatically reduces the A/D conversion frequency from GHz to MHz frequencies. Design strategy, applications and for the very first time, measurements are presented.

Design of a Miniaturized Wireless Blood Pressure Sensing Interface Using Capacitive Coupling

This paper presents the implementation of a miniaturized wireless blood pressure sensor interface. The system uses capacitive coupling in order to transmit the data, as well as wireless inductive powering. Designed for a bit length of 6.4 μs, the average power consumption of the device has been measured to be 20.5 μW and 2.85 mW in air and phantom material, respectively. The miniaturized sensor interface circuit consists of two plates with a diameter of 2.5 cm, which are connected by means of a thin wire; the devices maximum thickness is 5 mm.

65nm CMOS Circuit design of a sampled analog signal processor dedicated to RF applications

The software-defined radio (SDR) concept aims at designing a re-configurable radio architecture accepting all cellular or non-cellular standards working in the 0-5 GHz frequency range. Some technical challenges have to be solved in order to address this concept. A fully digital SDR system implying an A/D conversion close to the antenna is not feasible in the case of mobile terminal. This paper presents the design of an analog processor which process RF signal in order to elect and convert into digital only the desired RF signal envelope. It uses the principle of a fast Fourier transform (FFT) to carry out basic analog functions with high accuracy at a low power consumption. Schematic and post layout simulations are exhibited. Estimated die area and power consumption are numbered.

A 65-nm CMOS DAC Based on a Differentiating Arbitrary Waveform Generator Architecture for 5G Handset Transmitter

The data rate expected for the forthcoming 5G standard induces stringent constraints for handset transceivers. Wideband carrier aggregation will be handled with flexible and low-power architectures implemented in low-cost technologies. An architecture of a wideband signal generator intended to target sub-6-GHz 5G transmission requirements is presented. The architecture is based on a differential pulse code modulation coding scheme and a custom integrating DAC named the Riemann pump. It performs a 9-dB improvement of the signal-to-noise ratio per doubling of the oversampling ratio while ensuring a flat quantization noise floor over the whole multigigahertz conversion band. Its inherent ability to generate synchronous signals allows us to address carrier aggregation purposes; the generation of 10 synchronized 64-QAM modulated signals between 1.8 and 3.6 GHz is simulated. Postlayout simulations of the Riemann pump implemented in 65-nm CMOS technology fit the exposed theoretical features with a submilliwatt-level power consumption.

From Software-Defined to Software Radio: Analog Signal Processor features

The RF transceivers architectures are to integrate the concept of Sotware Radio. But, in the case of mobile terminal, hard constraints are imposed by the factor of mobility. Low power and very complex circuits are claimed by the telecommunication industry. Classical architectures are no more sufficient to challenge this goal. New systems are thus proposed, and the concept of Software Defined Radio (SDR) is a step on the roadmap toward Software Radio (SR). This paper presents a state of the art of SDR circuits and explores the application of a Analog Signal Processor SR chip.

The Riemann pump: A concurrent transmitter in GaN technology

An original arbitrary waveform generator (AWG) architecture suited for software radio (SR) transmission is presented. A piecewise linear approximation of the wanted signal is generated thanks to a predefined set of slopes. The digital-to-analog (DA) conversion involved in this operation is based on a differential digital coding which drives a custom digital-to-analog converter (DAC), named here the Riemann Pump. This circuit is in charge of outputting the piecewise linear signal by integration of current steps into a capacitive load, potentially being the input impedance of a power amplifier. Simulations have been carried out on a first design, developed in a GaN technology, with a configuration that covers 1 GHz bandwidth with an oversampling ratio (OSR) of 4 and 3 input bits. The generation of concurrent modulated signals is demonstrated, with a rejection of 30 dBr over the whole band. The system exhibits promising performances as for the realization of a multi-standard concurrent radio frequency transmitter with moderate hardware complexity.

A software-defined radio based on sampled analog signal processing dedicated to digital modulations

Telecommunication industry claims for a one-chip radiofrequency receiver. It is called Software Defined Radio (SDR). It is a re-configurable radio architecture accepting all the cellular or non-cellular standards working in a 0-5 GHz frequency range. A fully digital circuit could be the salvation. But, the analog to digital conversion and the digital operations face issues like power supply and processing speed. To overcome this technological bottleneck, a pre-processing circuit is interfaced between the antenna and a Digital Signal Processor (DSP) to pre-condition the RF signal. This paper presents the design of an analog discrete-time device located between the antenna and a DSP in standard radio architecture. It uses the principle of the Discrete Fourier Transform (DFT) to reduce the frequency of the DSP-input-signal treatment to fulfil the SDR purpose. An application to RF digital modulation is exhibited.