Yoan Veyrac

A 65-nm CMOS DAC Based on a Differentiating Arbitrary Waveform Generator Architecture for 5G Handset Transmitter

The data rate expected for the forthcoming 5G standard induces stringent constraints for handset transceivers. Wideband carrier aggregation will be handled with flexible and low-power architectures implemented in low-cost technologies. An architecture of a wideband signal generator intended to target sub-6-GHz 5G transmission requirements is presented. The architecture is based on a differential pulse code modulation coding scheme and a custom integrating DAC named the Riemann pump. It performs a 9-dB improvement of the signal-to-noise ratio per doubling of the oversampling ratio while ensuring a flat quantization noise floor over the whole multigigahertz conversion band. Its inherent ability to generate synchronous signals allows us to address carrier aggregation purposes; the generation of 10 synchronized 64-QAM modulated signals between 1.8 and 3.6 GHz is simulated. Postlayout simulations of the Riemann pump implemented in 65-nm CMOS technology fit the exposed theoretical features with a submilliwatt-level power consumption.

The Riemann pump: A concurrent transmitter in GaN technology

An original arbitrary waveform generator (AWG) architecture suited for software radio (SR) transmission is presented. A piecewise linear approximation of the wanted signal is generated thanks to a predefined set of slopes. The digital-to-analog (DA) conversion involved in this operation is based on a differential digital coding which drives a custom digital-to-analog converter (DAC), named here the Riemann Pump. This circuit is in charge of outputting the piecewise linear signal by integration of current steps into a capacitive load, potentially being the input impedance of a power amplifier. Simulations have been carried out on a first design, developed in a GaN technology, with a configuration that covers 1 GHz bandwidth with an oversampling ratio (OSR) of 4 and 3 input bits. The generation of concurrent modulated signals is demonstrated, with a rejection of 30 dBr over the whole band. The system exhibits promising performances as for the realization of a multi-standard concurrent radio frequency transmitter with moderate hardware complexity.

Full Software Radio transceivers

This paper presents the current status and trends in research on Full Software Radio (FSR). Concerning the receiver path after defining Software Defined Radio (SDR) versus FSR a new version of the Sampled Analog Signal Processor (SASP) is presented and experimental results are discussed. The new version doubles the signal bandwidth while the power consumption is reduced to less than 100 mW. For the transmitter path, a new FSR architecture is presented based on Riemanns algorithm and a charge pump. A GaN demonstrator of the Riemanns Pump is presented, which generates any signal including concurrent emissions in the 0-to-1 GHz band.

Experimental demonstration of a Riemann Pump RF-DAC in 65 nm CMOS

This article presents the first experimental results of an integrating Radio-Frequency DAC (RF-DAC) we called the Riemann Pump. This DAC is part of a complete waveform generator architecture based on the quantization of the signal variations and the conversion of the as-obtained digital signal into the analog domain. This technique provides an improvement of the coding efficiency with respect to conventional pulse code modulation conversion schemes. Measurement results confirm the feasibility of this novel topology into silicon CMOS technologies. The conversion efficiency of the prototype realized in 65 nm CMOS is as low as 12 fJ per conversion step.

Ultra-low power frequency synthesizer based on a dual-locking ring oscillator

An ultra-low power frequency synthesizer based on a 28-nm CMOS dual-voltage controlled ring oscillator is presented. The technological dispersion and temperature effects are tackled thanks to a Delay locked loop (DLL) which sets a coarse tuning voltage. A back-gate fine tuning voltage is used to lock the oscillating signal on a pure reference with a Phase locked loop (PLL). The close-in intrinsically-poor phase noise of the ring oscillator is cleaned up by the PLL. The overall system consumes less than 100µW to generate a 2.5GHz signal.

Toward 5 G: An integrated CMOS wide band arbitrary waveform generator for carrier aggregation

A wide band arbitrary waveform generator which targets sub-6 GHz 5G carrier aggregated transmission schemes is presented. The wanted signal is composed of up to ten aggregated modulated signals distributed over different frequency bands. A piecewise linear approximation of this composite signal is generated, based on the integration of constant current steps into a capacitive load. The implementation of the digital-to-analog core in a 65 nm CMOS technology is depicted; it exhibits a sub-mW consumption and a tiny die area. System simulations are led to confirm its ability to address the generation of various configurations of carrier aggregated signals with respect to the 5G prospects.