Sara Carniello

Through Silicon Via Reliability

Vertical integration of diverse semiconductor technologies can be achieved by utilizing interconnections through entire silicon substrates, known as through silicon vias (TSVs). TSVs present an interesting case study for reliability evaluation, given the particular fabrication technologies, geometries, and potential failure modes associated with such structures. A specific TSV technology is introduced, and key parameters for reliability assessment, such as residual stress, resistance, leakage, and dielectric breakdown, are discussed. Reliability data are presented, including the characterization of TSV parameters as a function of various accelerated lifetime stress tests, as well as assessments of the density and impact of TSV manufacturing defects. The presented data demonstrate that while the TSV is inherently quite robust, latent manufacturing defects pose a significant risk to long-term reliability. Screening methodologies, defect modes, failure analysis methods, process improvement, and correspondingly improved defect density results are discussed. The results are considered pertinent to the development and reliability of novel 3-D integrated process technologies.

Interface traps density-of-states as a vital component for hot-carrier degradation modeling

We refine our approach for hot-carrier degradation modeling based on a thorough evaluation of the carrier energy distribution by means of a full-band Monte–Carlo simulator. The model is extended to describe the linear current degradation over a wide range of operation conditions. For this purpose we employ two types of interface states, either created by single- or by multiple-electron processes. These traps apparently have different densities of states which is important to consider when calculating the charges stored in these traps. By calibrating the model to represent the degradation of the transfer characteristics, we extract the number of particles trapped by both types of interface traps. We find that traps created by the single- and multiple-electron mechanisms are differently distributed over energy with the latter shifted toward higher energies. This concept allows for an accurate representation of the degradation of the transistor transfer characteristics.

Hot-carrier degradation modeling using full-band Monte-Carlo simulations

We propose and verify a model for hot carrier degradation based on the exhaustive evaluation of the energy distribution function for charge carriers in the channel by means of a full-band Monte-Carlo device simulator. This approach allows us to capture the interplay between “hot” and “colder” electrons and their contribution to the damage build-up. In fact, particles characterized by higher energy are able to produce interface traps by a single-carrier process while colder ones trigger multivibrational mode excitation of a Si-H bond. For the model validation we use long-channel MOSFETs and represent the degradation of the linear drain current. The single-carrier component dominates degradation (this is the usual tendency for long devices), however, the multiple-carrier process is still considerable being less and less pronounced as the source-drain stress voltage increases

Passivation integrity investigations for through wafer interconnects

Through wafer interconnects (TWI) with diameters greater than 50 mum have the advantage of extremely low contact resistances. The mechanics of the layers inside the TWI has to be well understood order to avoid passivation cracks. Results of simulation and mechanical investigations are discussed in this paper.

Hot carrier stress degradation modes in p-type high voltage LDMOS transistors

The hot carrier stress induced device degradation of a p-type LDMOS high voltage transistor is investigated at different stress conditions. The influence of shallow trench corner rounding and carbon ion implantation into the shallow trench region is discussed. Numerical device simulations, charge pumping measurements and electrical characterisations are used for these investigations.

Effects of Bosch scallops on metal layer stress of an open Through Silicon Via technology

Through Silicon Via (TSV) is a lead topic in interconnects and 3D integration research, mainly due to numerous anticipated advantages. However, several challenges must still be overcome if large scale production is to be achieved. In this work, we have studied effects of Bosch scallops concerning mechanical reliability for a specific TSV technology. The presence of scallops on the TSV wall modifies the stress distribution along the via. By means of Finite Element Method (FEM) simulations, we could assess this change and understand the process. The achieved results support experiments and give a better insight into the influence of scallops on the stress in an open TSV.

Intrinsic stress analysis of tungsten-lined open TSVs

Abstract The effects of silicon etching and subsequent metallization during the fabrication of tungsten-lined open TSVs are examined using a combination of measurements and simulations. The total stress through a tungsten film deposited on a flat wafer is measured and finite element simulations are performed in order to identify the intrinsic and thermal stress components in the film. The data is then used to observe and model the stress through a TSV structure, which is etched using the DRIE process, resulting in scalloped inner sidewalls through the TSV opening. The scalloped structure is then compared to the ideal flat alternative with regard to the stress through the metal film and the TSVs electrical parameters, including resistance, capacitance, and inductance. It is found that the stress around the scallop varies significantly while the average stress through the tungsten in the flat TSV is only slightly higher than the stress observed through the scalloped structure. The resistance, capacitance, and inductance are all found to increase in the presence of scallops.

Analysis of hot carrier effects in a 0.35 μm high voltage n-channel LDMOS transistor

This paper presents the results of hot carrier stress experiments of a high voltage 0.35 μm n-channel lateral DMOS transistor. The stress induced degradation was investigated at different ambient temperatures over a wide range of both gate- and drain-stress voltages. In order to explain the observed device degradation under these stress conditions, the combined influence of hole- and electron induced degradation have to be taken into account. A physical explanation of the observed effects is provided and a phenomenological degradation model is suggested.

Analysis of worst-case hot-carrier conditions for high voltage transistors based on full-band monte-carlo simulations

Using a physics-based model for hot-carrier degradation we analyze the worst-case conditions for long-channel transistors of two types: a relatively low voltage n-MOSFET and a high-voltage p-LDMOS. The key issue in the hot-carrier degradation model is the information about the carrier energetical distribution function which allows us to asses the carrier acceleration integral determining the interface state build-up and which controls the interplay between the single- and multiple-carrier mechanisms of Si-H bond rupture. To analyze the worst-case conditions we generate intensity maps, i.e. dependences of some crucial quantities on source-drain Vds and gate Vgs stress voltage. These quantities are the boundary of the high-energy tail of the energy distribution function, the interface state generation rate and the total dose of degradation. The difference between positions of severest degradation spots evaluated according different criteria is also plotted as a function of stress voltages. Using these maps we demonstrate that the worst-case conditions are realized at 0.4Vds < Vgs < 0.5Vds for the n-MOSFET and at the maximal gate current for p-LDMOS. These findings correspond to experimental results published in the literature.

3D-Resurf: The integration of a p-channel LDMOS in a standard CMOS process

This paper presents an isolated high voltage (HV) p- channel lateral double diffused MOS (LDMOS) transistor integrated in a commercial 0.35mum CMOS process without any additional mask or implant steps and thus without increasing process complexity. It is shown that by the introduction of carefully controlled PWELL stripes in the drift region, an increase in breakdown voltages (VB) of LDMOS transistors from 10 to up to 25 V can be achieved. For the huge field of power management and automotive applications this approach of integration allows optimization for multiple voltage domains and guarantees high quality levels at an economical price level.