Harold Philipsen

Scalable Through Silicon Via with polymer deep trench isolation for 3D wafer level packaging

A scalable generic Through Silicon Via (TSV) process is developed using spin-on dielectric polymer as isolation layer where deep annular trenches in Silicon are filled with the polymer. Following parameters are found to be affecting the polymer material spreading on the wafer surface and the filling performance: pre-treatments on the wafer surface, TSV density and physical properties of the polymer. Yielding TSV chains are measured on the fabricated wafers and the TSV resistance is found to be ≪100mΩ. It is a via-last TSV process which is applicable to any silicon technology.

Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers

The establishment of a cost-effective Through Silicon Vias (TSV) fabrication process integrated to a CMOS flow with industrially available tools is of high interest for the electronics industry because such process can produce more compact systems. We present a 300mm industry-compliant via-middle TSV module, integrated to an advanced high-k/metal gate CMOS process platform. TSVs are fabricated by a Bosch process after contact fabrication and before the first metal layer. The target for copper diameter is 5μm and via depth in the silicon substrate is 50μm. Dense structures have a pitch of 10μm. The vias are filled with TEOS/O3 oxide to reduce via-to-substrate capacitance and leakage, a Ta layer to act as Cu-diffusion barrier and electroplated copper. Copper is thermally treated before CMP to minimize copper pumping effects. The processing is integrated as part of a 65nm node CMOS fabrication module and validated with regular monitoring of physical parameters. The module was tested in device lots and also integrated to a thinning and backside passivation flow.

3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias

In this paper, we report on the processing and the electrical characterization of a 3-D-wafer level packaging through-silicon-via (TSV) flow, using a polymer-isolated, Cu-filled TSV, realized on thinned wafers bonded to temporary carriers. A Cu/Sn micro-bump structure is integrated in the TSV process flow and used for realizing a two-die stack. Before TSV processing, the Si wafers are bonded to temporary carriers and thinned down to 50 μm. The actual TSV and micro-bump process uses 3 masks, two Si-deep-reactive ion etching steps and a polymer liner as a dielectric. The dimensions of the TSV structure are: 35 μm ØTSV, 5 μm thick polymer liner, 25-μm-Ø Cu TSV, 50 μm deep TSV, and a 60 μm TSV pitch.

Impact of post-plating anneal and through-silicon via dimensions on Cu pumping

Irreversible extrusion of Cu from through-silicon vias (TSVs) during high-temperature processing steps presents an important potential back-end-of-line (BEOL) reliability issue. Commonly this reliability risk is mitigated by introducing an anneal after Cu plating for TSV fill. This paper presents the impact of the post-plating anneal temperature and time on residual Cu pumping during a sinter for 20 min at 420 °C, for two different TSV dimensions. Using optical profilometry, in total ~ 4000 TSVs were measured, allowing detailed statistical analysis. Within one sample the Cu pumping values were found to be log normally distributed, implying an intrinsically large spread. Lower residual Cu pumping values were found in TSVs annealed at higher temperatures and for longer times, with the sinter conditions of 20 min at 420 °C confirmed as optimal post-plating anneal conditions. The larger TSVs showed more pumping in the average TSV, but at the tail of the distribution the Cu pumping behavior was the same as for the smaller TSVs. This implies that the impact of Cu pumping on BEOL reliability is identical for both sets of TSV dimensions, suggesting that the impact of Cu pumping on BEOL reliability is not necessarily reduced by reducing TSV dimensions.

Correlation between Cu microstructure and TSV Cu pumping

Cu pumping is the irreversible extrusion of Cu from Cu-filled through-silicon vias (TSVs) exposed to high temperatures during back-end of line (BEOL) processing. The distribution of Cu pumping values over the TSVs of a single wafer has a large intrinsic spread. As potential BEOL reliability issues due to Cu pumping will first occur at the highest pumping TSVs, they can be mitigated if the fundamental cause for this large intrinsic spread is known and under control. This paper describes a clear correlation between Cu pumping and TSV Cu microstructure based on the grain size at the top of 5×50 μm TSV, disregarding twin boundaries. For the mitigation of TSV Cu pumping the ideal microstructure was shown to consist of a single grain spanning the whole TSV cross section, bringing down the highest measured Cu pumping value from 248 nm to 73 nm. This effect was attributed to the absence of rapid diffusion paths and grain boundary sliding ability.

Void-Free Filling of HAR TSVs Using a Wet Alkaline Cu Seed on CVD Co as a Replacement for PVD Cu Seed

The results of a wet alkaline seed deposition process directly on a thin adhesion promoter film, such as chemical vapor deposition (CVD) Co, are presented. This solution has been successfully used for copper plating on blanket and patterned through-silicon-via (TSVs) wafers covered with either silicon oxide/physical vapor deposition (PVD) Ta/CVD Co or silicon oxide/PVD Ti/CVD Co stacks. Such direct plated films were used as seed layers for subsequent copper plating from an in-house-made acidic Cu bath with model additives poly(ethylene glycol) (PEG), bis(3-sulfopropyl) disulfide (SPS), and Janus Green B (JGB). We report the impact of the directly plated stack composition and thicknesses on the integration of the wet alkaline seed in TSVs with 5 μm width and high aspect ratio (HAR) as high as 8:1. The conformal wet seed layer enables the achievement of a successful void-free filling using an in-house made acidic Cu bath with model additives (SPS, PEG, and JGB).

Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping

In this study, we report on the processing and the electrical characterization of a 3D-WLP TSV flow, using a polymer-isolated, Cu-filled TSV, realized on thinned wafers bonded to temporary carriers. A Cu/Sn microbump structure is integrated in the TSV process flow and used for realizing a two-die stack. Before TSV processing, the Si wafers are bonded to temporary carriers and thinned down to 50µm. The actual TSV and microbump process uses 3 masks, two Si-DRIE steps and a polymer liner as a dielectric. The dimensions of the TSV structure are: 35µm Ø TSV, 5µm thick polymer liner, 25µm Ø Cu, 50µm deep TSV, and a 60µm TSV pitch.

Enhanced barrier seed metallization for integration of high-density high aspect-ratio copper-filled 3D through-silicon via interconnects

Higher performance, higher operation speed and volume shrinkage require high 3D interconnect densities. A way to meet the density specifications is to further increase the A.R. of the TSV interconnection. This requires the integration of highly conformal thin films deposition techniques in TSV flows, particularly for metallization. In this study, seed layer enhancement is applied to regular PVD Cu seed for metalizing TSV of diameter of 2μm and aspect-ratio 15:1. The results reported in this paper open a new path for process integration of high A.R. TSVs and provide a versatile and reliable building block for achieving the high density interconnects required for tomorrows 3D electronics devices.

High frequency scanning acoustic microscopy applied to 3D integrated process: Void detection in Through Silicon Vias

Among the technological developments pushed by the emergence of 3D-ICs, Through Silicon Via (TSV) technology has become a standard element in device processing over the past years. As volume increases, defect detection in the overall TSV formation sequence is becoming a major element of focus nowadays. Robust methods for in-line void detection during TSV processing are therefore needed especially for scaled down dimensions. Within this framework, the current contribution describes the successful application of innovative GHz Scanning Acoustic Microscopy (SAM) to TSV void detection in a via-middle approach.

High Efficiency Silver-Free Heterojunction Silicon Solar Cell

In this work, we present the results of the replacement of silver screen printing on heterojunction crystalline silicon (c-Si) solar cells with a copper metallization scheme that has the potential to reduce the manufacturing cost while improving their performance. We report for the first time silver-free heterojunction c-Si solar cells on 6-in. wafers. The conversion efficiency reached is a record 22.1% for c-Si technology for this wafer size (Voc = 729 mV, Jsc = 38.3 mA/cm2, FF= 79.1%). The total power generated is more than 5 W for 1-sun illumination, which is a world record. Heat-damp reliability tests show comparable performance for mini-modules fabricated with copper metalized as for conventional silver screen printed heterojunction c-Si solar cells.