G. Caiulo

An analog high-speed wide-range programmable monostable multivibrator

This paper presents a scheme for an analog monolithic monostable multivibrator suitable for use in a wide variety of applications where a need exists for pulses of a known and precise width in response to a trigger signal. The pulse can be programmed either using a reference current or an external capacitor which allow widths from 5 ns to a maximum which is limited only by capacitor values availability. The circuit was fabricated in a standard 1.2 /spl mu/m BiCMOS technology, but it is shown to be fully CMOS compatible. Measurement results indicate that very high speed is obtained at very low power dissipation and cost.

A 30-mW 10.7-MHz pseudo-N-path sigma-delta band-pass modulator

This paper presents a sigma-delta modulator designed to convert band-pass signals for digital radio and cellular telephony. The proposed architecture employs only one operational amplifier, thus allowing a reduction of power consumption. A prototype implemented in a 1.2-/spl mu/m double-poly double-metal BiCMOS technology exhibits an SNR equivalent to 8 bits of resolution over a 200-kHz band, and dissipates only 30 mW with a 5-V supply.

Novel circuit solutions for rail-to-rail CMOS buffer

The design of low-power rail-to-rail output buffers for high capacitive loads is critical. In particular, control of the output current, constant input transconductance and output stage driving must be well confined. In this paper we discuss the major design constraints and present a new topology for a CMOS rail-to-rail output buffer. The experimental results show that the proposed architecture is suitable for input-output signals within the full dynamic.

Active compensation of parasitic capacitances in a 10 bit 50 MHz CMOS D/A converter

A novel method for the active compensation of parasitic capacitances in high speed resistor string D/A converters is described. The experimental results obtained from a 10 bit DAC show that the approach proposed is essential to the achievement of a 50 MHz clock rate when using commercial 1.2 /spl mu/m CMOS analog technology.<<ETX>>

Analog blocks for high-speed oversampled A/D converters

The design of high performance sigma-delta converters involves high frequency operation. This constraint means analog blocks must be carefully designed to meet these requirements. BiCMOS technology offers advantages with respect to CMOS in realising high-speed analog blocks. This paper describes an operational amplifier and a comparator designed in BiCMOS technology. Suitable circuit solutions have been used to obtain the required values for DC gain, gain-bandwidth product and slew-rate. High-level simulations of both low-pass and band-pass oversampled converters indicate that the blocks designed allow a faster clock rate than CMOS and are suitable for operation in switched-capacitor circuits with sampling rate of up to 40 MHz.

Design of high-accuracy video comparator

The design of high-accuracy high-frequency comparators needs particular care especially with parameters such as offset and overdrive recovery. This paper discusses the major design constraints and presents a new topology for a CMOS video comparator. The experimental results show that the proposed architecture is suitable for use in high-performance A/D converters.<<ETX>>

Active compensation of parasitic capacitances for very high frequency CMOS DACs

High frequency digital-analog (DACs) requiring an output buffer find a speed limitation in the overall input capacitive load of the buffer. An active scheme for the compensation of such a load, including the parasitic capacitances coming from reversely biased junctions associated with analog switches is presented. Computer simulations on a given architecture (10-b DAC) show the effectiveness of the proposed approach.<<ETX>>

Waveform shaping for GSM systems

This paper describes a new integrated topology circuit for a waveform shaper which will be used inside a GSM system. The circuit generates a raised cosine shape output for the ramp up and ramp down of a transmitted burst. The circuit was realised using two 8-bit current-steering digital-to-analog converters. The measured results of the transient spectrum and the power level versus time show that the circuit fully meets GSM specifications.

High speed and high performance signal processing for nuclear electronics

A vast amount of signal processing will soon be required in close proximity to high-energy physics detectors. The challenge is to transfer conventional electronics to VLSI technologies. This paper discusses the present trends in nuclear electronics and presents integrated realisations of two processing systems commonly used in high-energy physics experiments: a discriminator and a charge-to-time converter. The chips, fabricated in 1.2 /spl mu/m BiCMOS technology, feature high speed of operation and high-quality processing performance combined with reduced silicon area and power consumption.

A High Frequency CMOS Power Buffer with Extended Linearity

A CMOS power buffer suitable for high frequency applications is discussed. The use of a high-speed push-pull output stage and a highly-linear common mode feedback allow good linearity to be maintained even with very high input frequencies. Indeed, Total Harmonic Distortions (THD) as good as ¿66 dB and ¿58 dB are achieved at 0.5 MHz and 1 MHz, respectively, with a load resistance of 75 ¿. Moreover, the circuit provides a dc gain of 62 dB and a gain-bandwidth product of 60 MHz. The integrated prototype, realized using a 1.2 ¿m CMOS process, occupies a silicon area of 280 mils2.