G. Ghibaudo

A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with Gate-All-Around or independent gates (φ-Flash), suitable for full 3D integration

We present the first experimental study of a Gate-All-Around (GAA) SONOS memory architecture with 4-level crystalline nanowire channels (down to 6nm-diameter). The technology is also extended to an independent double gate memory architecture, called φ-Flash. The experimental results with 6nm nanowires show high programming windows (up to 7.4V), making the structure compatible with multilevel operation. Excellent retention even after 104 cycles is achieved. The independent double gate option has otherwise been successfully integrated with 4-level stacked nanowires for multibit applications. The φ-Flash exhibits up to 1.8V ΔVTh between its two gates, demonstrating multibits operation. The basic process to fully disconnect the different nanowires in view of a full 3D integration of a memory array is discussed.

Experimental and theoretical investigation of nano-crystal and nitride-trap memory devices

In this paper, we propose a thorough experimental and theoretical investigation of memory-cell structures employing discrete-trap type storage nodes, using either natural nitride traps or semiconductor nano-crystals. thus operating with a small finite number of electrons. A detailed account of static and dynamic charging/discharging phenomena occurring in these devices is given, based on bias-, time-, and temperature-dependent measurements. A comprehensive interpretation of experimental results is proposed by means of physical modeling. In particular, two different models are proposed. The first one consists in a modified floating-gate-like approach, while the second one is a trap-like approach, relying on Shockley-Read-Hall statistics. Using these two approaches, some general behavior laws for memory operation are formulated. Considerations on the suitability of each model on the particular structures are suggested.

Improved split C-V method for effective mobility extraction in sub-0.1-/spl mu/m Si MOSFETs

The feasibility of split capacitance-voltage (C-V) measurements in sub-0.1 /spl mu/m Si MOSFETs is demonstrated. Based on the split C-V measurements, an improved methodology to extract accurately the effective channel length and the effective mobility is proposed. Unlike conventional I/sub d/(V/sub g/)-based extraction techniques, this new approach does not assume the invariance of the effective mobility with gate length (assumption proved to be false in this paper). This method is relevant to study transport limitations in ultimate MOSFETs as illustrated with the study of pocket implant influence on 50-nm p-MOSFETs.

Characterization and modeling of hysteresis phenomena in high K dielectrics

An original technique for the dynamic analysis of Id(Vg) hysteresis on high K stacks is proposed, allowing the characterization of Vt shift transients at short times. The experimental results demonstrate that trapping/de-trapping mechanism by tunneling from the substrate must be considered. Furthermore, a new model based on a trap-like approach is successfully developed to interpret the dependence of hysteresis phenomena with high k gate stack architecture.

75 nm damascene metal gate and high-k integration for advanced CMOS devices

An advanced CMOS process has been proposed which include key features: 75 nm gate length damascene metal gate, high-k dielectrics with 1.35 nm EOT. Detailed characterisation (TEM, C-V, split C-V, charge pumping, LF noise, low and high temperature transport) demonstrate the high quality of the dielectric and interface. Low Ioff and low gate current make the technology attractive for low standby power applications.

15nm-diameter 3D stacked nanowires with independent gates operation: ΦFET

For the first time, we report a 3D stacked sub-15 nm diameter NanoWire FinFET-like CMOS technology (3D-NWFET) with a new optional independent gate nanowire structure named PhiFET. Extremely high driving currents for 3D-NWFET (6.5 mA/mum for NMOS and 3.3 mA/mum for PMOS) are demonstrated thanks to the 3D configuration using a high-k/metal gate stack. Co-processed reference FinFETs with fin widths down to 6 nm are achieved with record aspect ratios of 23. We show experimentally that the 3D-NWFET, compared to a co-processed FinFET, relaxes by a factor of 2.5 the channel width requirement for a targeted DIBL and improves transport properties. PhiFET exhibits significant performance boosts compared to Independent-Gate FinFET (IG-FinFET): a 2-decade smaller IOFF current and a lower subthreshold slope (82 mV/dec. instead of 95 mV/dec.). This highlights the better scalability of 3D-NWFET and PhiFET compared to FinFET and IG-FinFET, respectively.

How far will silicon nanocrystals push the scaling limits of NVMs technologies

For the first time, memory devices with optimized high density (2E12#/cm/sup 2/) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell up to 1 Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND flash at least to the 35 nm and 65 nm nodes, respectively.

Experimental and comparative investigation of low and high field transport in substrate- and process-induced strained nanoscaled MOSFETs

We report a detailed comparison of low and high-Vd transport between various substrate- and process-induced strained MOSFETs down to 40nm gate lengths. Thanks to an original extraction method and low temperature measurements, we demonstrate that the mobility behaviour is deeply impacted by the down-scaling because of Coulomb scattering. Introducing this behaviour into a saturation current model, we clearly explain the I/sub ON/ enhancement trend of all strained devices.

Single electron effects and structural effects in ultrascaled silicon nanocrystal floating-gate memories

In this paper, we present a nanometer-sized floating-gate memory device, fabricated on silicon-on-insulator substrate and using silicon nanocrystals as storage nodes. Single electron charging and discharging phenomena occurring at room temperature will be demonstrated and discussed by means of simple analytical models. A deeper investigation of the impact of critical dimensions of the memory cell (i.e., active area and channel width and length) on the device operation (in particular, memory programming window), performed on a large number of samples, will be reported. Qualitative explanations for the observed experimental behaviors will be given.

3DVLSI with CoolCube process: An alternative path to scaling

3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm2. This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube™ technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization.