J-M. Portal

Evaluation of OxRAM cell variability impact on memory performances through electrical simulations

An investigation in the impact of Oxide-based Resistive Memory RAM devices (OxRRAM) variability on the memory array performances is proposed. Variability in advanced IC designs has emerged as a roadblock and significant efforts of process and design engineers are required to decrease its impact. This is especially true for OxRRAM memory, combining high level of integration with exotic materials. In this study, electrical simulations, based on an OxRRAM compact model, are performed at a circuit level. Simulation results are analyzed in terms of OxRRAM cells electrical characteristic variations to evaluate the robustness of the memory array.

Development of a CMOS Oscillator Concept for Particle Detection and Tracking

An oscillator concept developed for particle detection and tracking is presented. The methodology used to characterize the currents generated by the particle is detailed. A Design Of Experiment (DOE) analysis is used to correlate the circuit oscillations with the current characteristics after particle detection. To validate the concept, an application example is developed to validate the detector capability to track a striking particle.

SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures

Passive crossbar memories based on resistive switching bit-cells are today seen as the most promising candidates for flash memories replacement. However, inherent sneak currents through unselected devices lead to low operating margins and over-consumption during read and programming operations. Crossbar memory simulations with bit-cells based on two terminal nonlinear selectors, also show degraded performances due to sneak path currents, leading to nonfunctional memories. Thus, peripheral circuits have to be designed in order to mitigate the sneak currents that impact memory operations. In this paper, we propose a dynamic sneak current compensation circuit for SET and read operations, enabling multi-level cell programming. This circuit is simulated using CMOS 130nm Bulk core process with OxRAM and tunnel barrier-based selector bit-cell.

Analysis of SEU parameters for the study of SRAM cells reliability under radiation

A simplified RC circuit is used to simulate the effects of ionizing particles in a 90nm SRAM. The main characteristic of the memory cell bit flip are discussed and compared for characteristic parameters. The effect of the surrounded circuit on the impacted transistor is discussed in order to extract parameters characteristic of the SEU occurrence.

Current density aware algorithm for net generation in analog high current application

In deep submicron VLSI circuits, excessive current density in interconnects is a major concern for analog high current application. If current over maximum density is not effectively mitigated, this can lead to phenomena like electromigration, voltage drop and electrical overload. It is a hot topic of interest in modern circuits due to the decrease of metal track sizes while high currents are necessary in automotive or mobile applications. In this paper, an algorithm considering current constraints for net generation is presented. It determines all branch currents and proposes a routing for signal nets with current-dependent wire width. First, the phenomena of electromigration and voltage drop are introduced. The current constrained wire planning algorithm is presented and shows results improved on average by about 10% for area and almost 27% for CPU time compared with existing solution.

Impact of SEU configurations on a SRAM cell response at circuit level

This work focuses on the SEU simulation in a 90nm SRAM cell, in order to provide basic metrics for reliability studies. To do that, a charge generation model is used to simulate the impact of an ionizing particle striking a sensitive node. The current collected at this particular node is extracted and injected at a circuit level. Thus, a correlation between the circuit electrical behavior and the critical charge is presented.

A novel flash EEPROM diagnosis methodology based on I–V signatures extraction

The objective of this paper is to present a flash EEPROM memory diagnosis methodology based on I-V cell characteristics extraction. In this work, the root cause of any variation of the memory cell IN characteristic is investigated. Thus, this method allows to quickly diagnose any variation of the memory IN shape in terms of design parameters, process variability, electrical variations, bridge and open fault defects while maintaining the test cost acceptable. This novel technique is more efficient than conventional Flash EEPROM diagnosis techniques based on threshold voltage extraction (VT).

An efficient model to evaluate the impact of design parameters on charge pump circuits’ performances: Application on RFID circuits

In this paper a charge pump model based on a DOE (design of experiment) model generation technique is presented. The DOE technique takes as input electrical simulation results of a charge pump circuit for different component geometries and different oscillator pulse periods. It produces, as outputs, polynomial equations of the charge pump output voltage HV and the consumption current ISUNK. Using those equations, impact of specific charge pump design parameters on charge pump outputs is clearly shown. Thus, design guidelines can be followed to optimize charge pump circuits efficiency. To validate this approach, this optimization methodology is used to evaluate the charge pump optimal configuration of a low voltage and low current IC circuit (RFID tag).

A new adustable Schmitt Trigger based on Dual Control Gate-Floating Gate Transistor (DCG-FGT)

This paper presents a low voltage adjustable CMOS Schmitt trigger using DCG-FGT transistor. Simple circuit is introduced to provide flexibility to program the hysteretic threshold in this paper. The hysteresis can be controlled accurately at a large voltage range. The proposed Schmitt trigger has been designed using 90nm 1.2V CMOS technology and simulated using Eldo with PSP device models. The simulation results show rail-to-rail operation and independently adjustable switching voltages VTH- (low switching voltage) and VTH+(high switching voltage).

Impact of a laser pulse on HfO2-based RRAM cells reliability and integrity

Several NVM technologies have emerged during the last 10 years. These technologies offer solutions for the replacement of the Flash technology, which is facing downsizing limits [1]. Moreover these solutions propose lower switching energy and faster operations compared to the state of the art for Flash, and thus, are seen as an opportunity for the rise of the IoT market. But one of the main concerns regarding IoT is the protection of the data. Contrary to Flash, security of the data in emerging NVM is yet to be evaluated. In order to verify capability of the technology in terms of data integrity, we propose to investigate reliability and integrity of HfO2-based Resistive RAM (OxRRAM). This paper details the experimental protocol defined for laser-based attacks, shows that a laser pulse can affect the information stored in a single OxRRAM bit. The occurring phenomenon is then explained by mean of thermal and electrical simulations.